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参数资料
| 型号： | AD7244AQ |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | DAC |
| 英文描述： | LC2MOS Dual, Complete, 12-Bit/14-Bit Serial DACs |
| 中文描述： | DUAL, SERIAL INPUT LOADING, 2 us SETTLING TIME, 14-BIT DAC, CDIP24 |
| 封装： | 0.300 INCH, HERMETIC SEALED, CERDIP-24 |
| 文件页数： | 8/12页 |
| 文件大小： | 319K |
| 代理商： | AD7244AQ |
AD7242/AD7244
REV. A
–8–
TIMING AND CONTROL
Communication with the AD7242/AD7244 is via six serial logic
inputs. These consist of separate serial clocks, word framing and
data lines for each DAC. DAC updating is controlled by two
digital inputs:
LDACA
for updating V
OUTA
and
LDACB
for
updating V
OUTB
. These inputs can be asserted independently of
the microprocessor by an external timer when precise updating
intervals are required. Alternatively, the
LDACA
and
LDACB
inputs can be driven from a decoded address bus allowing the
microprocessor control over DAC updating as well as data
communication to the AD7242/AD7244 input latches.
The AD7242/AD7244 contains two latches per DAC, an input
latch and a DAC latch. Data must be loaded to the input latch
under the control of TCLKA,
TFSA
and DTA for input Latch
A and TCLKB,
TFSB
and DTB for input Latch B. Data is then
transferred from input Latch A to DAC Latch A under the control
of the
LDACA
signal, while
LDACB
controls the loading of DAC
Latch B from input Latch B. Only the data held in the DAC
latches determines the analog outputs of the AD7242/AD7244.
Data is loaded to the input latches under control of the respec-
tive TCLK,
TFS
and DT signals. The AD7242/AD7244
expects a 16-bit stream of serial data on its DT inputs. Data
must be valid on the falling edge of TCLK. The
TFS
input
provides the frame synchronization signal that tells the AD7242/
AD7244 that valid serial data will be available on the DT input
for the next 16 falling edges of TCLK. Figure 6 shows the
timing diagram for operation of either of the two serial input
ports on the part.
Although 16 bits of data are clocked into the input latch, only
12 bits are transferred into the DAC latch for the AD7242 and
14 bits are transferred for the AD7244. Therefore, 4 bits in the
AD7242 data stream and 2 bits in the AD7244 data stream are
don’t cares since their value does not affect the DAC latch data.
The bit positions are the don’t cares followed by the DAC data
starting with the MSB (see Figure 6).
The respective
LDAC
signals control the transfer of data to the
respective DAC latches. Normally, data is loaded to the DAC
latch on the falling edge of
LDAC
. However, if
LDAC
is held
low, serial data is loaded to the DAC latch on the sixteenth
falling edge of TCLK. If
LDAC
goes low during the loading of
serial data to the input latch, no DAC latch update takes place
on the falling edge of
LDAC
. If
LDAC
stays low until the serial
transfer is completed, then the update takes place on the sixteenth
falling edge of TCLK. If
LDAC
returns high before the serial
data transfer is completed, no DAC latch update takes place.
If seventeen or more TCLK edges occur while
TFS
is low, the
seventeenth (and beyond) clock edges are ignored, i.e., no
further data is clocked into the input latch after the sixteenth
TCLK edge following a falling edge on
TFS
.
Figure 6. AD7242/AD7244 Timing Diagram
相关PDF资料 |
PDF描述 |
|---|---|
| AD7242JN | LC2MOS Dual, Complete, 12-Bit/14-Bit Serial DACs |
| AD7243 | LC2MOS 12-Bit Serial DACPORT |
| AD7243AN | LC2MOS 12-Bit Serial DACPORT |
| AD7243AQ | LC2MOS 12-Bit Serial DACPORT |
| AD7243AR | LC2MOS 12-Bit Serial DACPORT |
相关代理商/技术参数 |
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