参数资料
型号: AD7245AAP
厂商: ANALOG DEVICES INC
元件分类: DAC
英文描述: LC2MOS 12-Bit DACPORTs
中文描述: PARALLEL, WORD INPUT LOADING, 7 us SETTLING TIME, 12-BIT DAC, PQCC28
封装: PLASTIC, LCC-28
文件页数: 2/16页
文件大小: 306K
代理商: AD7245AAP
A
2
Version
B
2
Version
T
2
Version
Parameter
Units
T est Conditions/Comments
ST AT IC PERFORMANCE
Resolution
Relative Accuracy @ +25
°
C
3
T
MIN
to T
MAX
T
MIN
to T
MAX
Differential Nonlinearity
3
Unipolar Offset Error @ +25
°
C
3
T
MIN
to T
MAX
Bipolar Zero Error @ +25
°
C
3
T
to T
DAC Gain Error
3, 6
Full-Scale Output Voltage Error
7
@ +25
°
C
±
0.2
Full Scale/
V
DD
Full Scale/
V
SS
Full-Scale T emperature Coefficient
8
12
±
3/4
±
1
12
±
1/2
±
3/4
±
1/2
±
1
±
3
±
5
±
2
±
4
±
2
±
0.2
±
0.06
±
0.01
±
30
12
±
1/2
±
3/4
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
% of FSR max
% of FSR/V max
% of FSR/V max
ppm of FSR/
°
C max
V
DD
= 15 V
±
5%
Guaranteed Monotonic
V
SS
= 0 V or –12 V to –15 V
4
T ypical T empco is
±
3 ppm of FSR
5
/
°
C.
R
connected to REF OUT ; V
= –12 V to –15 V
4
T ypical T empco is
±
3 ppm of FSR
5
/
°
C.
±
1
±
3
±
5
±
3
±
5
±
2
±
1
±
3
±
5
±
2
±
4
±
2
±
0.2
±
0.06
±
0.01
±
40
V
DD
= +15 V
V
DD
= +12 V to +15 V
4
V
SS
= –12 V to –15 V
4
V
DD
= +15 V
±
0.06
±
0.01
±
30
REFERENCE OUT PUT
REF OUT @ +25
°
C
REF OUT /
V
DD
Reference T emperature Coefficient
Reference Load Change
(
REF OUT vs.
I)
4.99/5.01 4.99/5.01
2
±
25
4.99/5.01 V min/V max
2
mV/V max
±
35
ppm/
°
C typ
V
DD
= +15 V
V
DD
= +12 V to +15 V
4
2
±
25
–1
–1
–1
mV max
Referenee Load Current Change (0–100
μ
A)
DIGIT AL INPUT S
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
Input Capacitance
9
2.4
0.8
±
10
8
2.4
0.8
±
10
8
2.4
0.8
±
10
8
V min
V max
μ
A max
pF max
V
IN
= 0 V to V
DD
ANALOG OUT PUT S
Output Range Resistors
Output Voltage Ranges
10
Output Voltage Ranges
10
15/30
+5, +10
+5, +10,
±
5
0.5
15/30
+5, +10
+5, +10,
±
5
0.5
15/30
+5, +10
+5, +10,
±
5
0.5
k
min/k
max
V
V
SS
= 0 V; Pin Strappable
V
SS
= –12 V to –15 V;
4
Pin Strappable
V
typ
DC Output Impedance
AC CHARACT ERIST ICS
9
Voltage Output Settling T ime
Positive Full-Scale Change
Negative Full-Scale Change
Output Voltage Slew Rate
Digital Feedthrough
3
Digital-to-Analog Glitch Impulse
Settling T ime to Within
±
1/2 LSB of Final Value
DAC Latch All 0s to All 1s
DAC Latch All 1s to All 0s; V
SS
= –12 V to –15 V
4
7
7
2
10
30
7
7
2
10
30
10
10
1.5
10
30
μ
s max
μ
s max
V/
μ
s min
nV-s typ
nV-s typ
POWER REQUIREMENT S
V
DD
+10.8/
+16.5
–10.8/
–16.5
9
10
3
+11.4/
+15.75
–11.4/
–15.75
9
10
3
+11.4/
+15.75
–11.4/
–15.75
9
12
5
V min/
V max
V min/
V max
mA max
mA max
mA max
For Specified Performance Unless Otherwise Stated
V
SS
For Specified Performance Unless Otherwise Stated
I
DD
@ +25
°
C
T
MlN
to T
MAX
I
SS
Output Unloaded; T ypically 5 mA
Output Unloaded
Output Unloaded; T ypically 2 mA
NOT ES
1
Power supply tolerance is
±
10% for A Version and
±
5% for B and T Versions.
2
T emperature ranges are as follows: A/B Versions; –40
°
C to +85
°
C; T Version; –55
°
C to +125
°
C.
3
See T erminology.
4
With appropriate power supply tolerances.
5
FSR means Full-Scale Range and is 5 V for the 0 V to +5 V output range and 10 V for both the 0 V to +10 V and
±
5 V output ranges.
6
T his error is calculated with respect to the reference voltage and is measured after the offset error has been allowed for.
7
T his error is calculated with respect to an ideal 4.9988 V on rhe 0 V to +5 V and
±
5 V ranges; it is calculated with respect to an ideal 9.9976 V on the
0 V to +10 V range. It includes the effects of internal voltage reference, gain and offset errors.
8
Full-Scale T C =
FS/
T , where
FS is the full-scale change from T
A
= +25
°
C to T
MIN
or T
MAX
.
9
Sample tested at +25
°
C to ensure compliance.
10
0 V to +10 V output range is available only when V
DD
+14.25 V.
Specifications subject to change without notice.
AD7245A/AD7248A–SPECIFICATIONS
AGND = DGND = OV, R
L
= 2 k
V
, C
L
= 1OOpF. All specifications T
MN
to T
MAX
unless otherwse noted.)
REV. A
–2–
(V
DD
= +12 V to +15 V,
1
V
SS
= OV or –12 V to –15 V,
1
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