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| 型号： | AD7262BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 16/33页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT W/PGA&COM 48-LFCSP |
| 标准包装： | 1 |
| 位数： | 12 |
| 采样率（每秒）： | 1M |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 120mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-VQ（7x7） |
| 包装： | 管件 |
| 输入数目和类型： | 2 个差分，单极 |
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AD7262
Rev. 0 | Page 22 of 32
MODES OF OPERATION
The AD7262/AD7262-5 allow the user to choose between two
modes of operation, pin-driven mode and control register mode.
PIN-DRIVEN MODE
In pin-driven mode, the user can select the gain of the PGA, the
power-down mode, internal or external reference, and initiate
a calibration of the offset for both ADC A and ADC B. These
functions are implemented by setting the logic levels on the gain
pins (G3 to G0), the power-down pins (PD2 to PD0), the REFSEL
pin, and the CAL pin, respectively.
The logic state of Pin G3 to Pin G0 determines which mode of
operation is selected. Pin-driven mode is selected if at least one
of the gain pins is set to a logic high state. Alternatively, if all
four gain pins are connected to a logic low, the control register
mode of operation is selected.
GAIN SELECTION
The on-board PGA allows the user to select from 14 program-
mable gain stages: ×1, ×2, ×3, ×4, ×6, ×8, ×12, ×16, ×24, ×32,
×48, ×64, ×96, and ×128. The PGA accepts fully differential
analog signals and provides three key functions, which include
selecting gains for small amplitude input signals, driving the
ADCs switched capacitive load, and buffering the source from
the switching effects of the SAR ADCs. The AD7262/AD7262-5
offer the user great flexibility in user interface, providing gain
selection via the control register or by driving the gain pins to
the desired logic state. The AD7262/AD7262-5 have four gain
pins, G3, G2, G1 and G0, as shown in Figure 3. Each gain setting
is selected by setting up the appropriate logic state on each of
the four gain pins, as outlined in Table 6. If all four gain pins are
connected to a logic low level, the part is put in control register
mode and the gain settings are selected via the control register.
Table 6. Gain Selection
G3
G2
G1
G0
Gain
0
Software control
via control register
0
1
0
1
0
2
0
1
3
0
1
0
4
0
1
0
1
6
0
1
0
8
0
1
12
1
0
16
1
0
1
24
1
0
1
0
32
1
0
1
48
1
0
64
1
0
1
96
1
0
128
POWER-DOWN MODES
The AD7262/AD7262-5 offer the user a number of power-down
options to enable individual device components to be powered
down independently. These options can be chosen to optimize
the power dissipation for different application requirements.
The power-down modes can be selected by either programming
the device via the control register or by driving the PD pins to
the appropriate logic levels. By setting the PD pins to a logic low
level when in pin-driven mode, all four comparators and both
ADCs can be powered down. The PD2 and PD0 pins must be
set to logic high and the PD1 pin set to logic low to power up all
circuitry on the AD7262/AD7262-5. The PD pin configurations
for the various power-down options are outlined in Table 7.
Table 7. Power-Down Modes
PD2
PD1
PD0
Comparator A,
Comparator B
Comparator C,
Comparator D
ADC A,
ADC B
0
Off
0
1
Off
On
0
1
0
Off
On
Off
0
1
On
Off
1
0
On
Off
1
0
1
On
11
Off
1 PD2 = PD1 = PD0 = 1 resets the AD7262/AD7262-5 when in pin-driven mode
only.
The AVCC and VDRIVE supplies must continue to be supplied to
the AD7262/AD7262-5 when the comparators are powered up
but the ADCs are powered-down. External diodes can be used
from the CA_CBVCC and/or CC_CDVCC to both the AVCC and the
VDRIVE supplies to ensure they retain a supply at all instances.
The AD7262/AD7262-5 can be reset in pin-driven mode only
by setting the PDx pins to a logic high state. When the device is
reset, all the registers are cleared and the four comparators and
the two ADCs are left powered down.
In normal mode of operation with the ADCs and comparators
powered on, the CA_CBVCC/CC_CDVCC supply and the AVCC
supply can be at different voltage levels, as indicated in Table 1.
When the comparators on the AD7262/AD7262-5 are in power-
down mode, and the CA_CBVCC/CC_CDVCC supplies are at a
potential 0.3 V greater than or less than the AVCC supply, the
supplies consume more current than would be the case if both
sets of supplies were at the same potential. This configuration
does not damage the AD7262/AD7262-5 but results in additional
current flowing in any or all of the AD7262/AD7262-5 supply
pins. This is due to ESD protection diodes within the device. In
applications where power consumption in power-down mode is
critical, it is recommended that the CA_CBVCC/CC_CDVCC supply
and the AVCC supply be held at the same potential.
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| AD7262BCPZ-5 | 功能描述:IC ADC 2CH 12BIT PGA/COM 48LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:16 采样率（每秒）:45k 数据接口:串行 转换器数目:2 功率耗散（最大）:315mW 电压电源:模拟和数字 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC W 包装:带卷 (TR) 输入数目和类型:2 个单端，单极 |
| AD7262BCPZ-5-RL7 | 功能描述:IC ADC 2CH 12BIT PGA/COM 48LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:16 采样率（每秒）:45k 数据接口:串行 转换器数目:2 功率耗散（最大）:315mW 电压电源:模拟和数字 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC W 包装:带卷 (TR) 输入数目和类型:2 个单端，单极 |
| AD7262BCPZ-RL7 | 功能描述:IC ADC 2CH 12BIT PGA/COM 48LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:16 采样率（每秒）:45k 数据接口:串行 转换器数目:2 功率耗散（最大）:315mW 电压电源:模拟和数字 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC W 包装:带卷 (TR) 输入数目和类型:2 个单端，单极 |
| AD7262BSTZ | 功能描述:IC ADC 2CH 12BIT PGA/COM 48LQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:12 采样率（每秒）:300k 数据接口:并联 转换器数目:1 功率耗散（最大）:75mW 电压电源:单电源 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC 包装:带卷 (TR) 输入数目和类型:1 个单端，单极；1 个单端，双极 |
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