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| 型号： | AD7264BSTZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/29页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT 2CH 1MSPS 48LQFP |
| 标准包装： | 1 |
| 位数： | 14 |
| 采样率（每秒）： | 1M |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 175mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 托盘 |
| 输入数目和类型： | * |
| 产品目录页面： | 777 (CN2011-ZH PDF) |
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Data Sheet
AD7264
Rev. B | Page 21 of 28
Power-Up Conditions
On power-up, the status of the gain pins determines which
mode of operation is selected, as outlined in the Gain Selection
section. All registers are set to 0.
If the AD7264 is powered up in pin driven mode, the gain pins
and the PD pins should be configured to the appropriate logic
states and a calibration initiated if required.
Alternatively, if the AD7264 is powered up in control register
mode, the comparators and ADCs are powered down and the
default gain is 1. Thus, powering up in control register mode
requires a write to the device to power up the comparators and
the ADCs.
It takes the AD7264 15 μs to power up when using an external
reference. When the internal reference is used, 240 μs are required
to power up the AD7264 with a 1 μF decoupling capacitor.
CONTROL REGISTER
The control register on the AD7264 is a 12-bit read and write
register that is used to control the device when not in pin driven
mode. The PD0/DIN pin serves as the serial DIN pin for the
AD7264 when the gain pins are set to 0 (that is, the part is not in
pin driven mode). The control register can be used to select the
gain of the PGAs, the power-down modes, and the calibration
of the offset for both ADC A and ADC B. When in the control
register mode of operation, PD1 and PD2 should be connected
to a low logic state. These functions can also be implemented by
setting the logic levels on the gain pins, power-down pins, and
CAL pin, respectively. The control register can also be used to
read the offset and gain registers.
Data is loaded from the PD0/DIN pin of the AD7264 on the
falling edge of SCLK when CS is in a logic low state. The control
register is selected by first writing the appropriate four WR bits,
as outlined in Table 10. The 12 data bits must then be clocked
into the control register of the device. Thus, on the 16th falling
SCLK edge, the LSB is clocked into the device. One more SCLK
cycle is then required to write to the internal device registers. In
total, 17 SCLK cycles are required to successfully write to the
AD7264. The data is transferred on the PD0/DIN line while the
conversion result is being processed. The data transferred on
the DIN line corresponds to the AD7264 configuration for the
next conversion.
Only the information provided on the 12 falling clock edges after
the CS falling edge and the initial four write address bits is loaded
to the control register. The PD0/DIN pin should have a logic low
state for the four bits RD3 to RD0 when using the control register
to select the power-down modes and gain setting, or when initia-
lizing a calibration. The RD bits should also be set to a logic low
level to access the ADC results from both DOUTA and DOUTB.
The power-up status of all bits is 0, and the MSB denotes the first
bit in the data stream. The bit functions are outlined in Table 9.
Table 8. Control Register Bits
MSB
LSB
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RD3
RD2
RD1
RD0
CAL
PD2
PD1
PD0
G3
G2
G1
G0
Table 9. Control Register Bit Function Descriptions
Bits
Mnemonic
Comment
11 to 8
RD3 to RD0
Register address bits. These bits select which register the subsequent read is from. See Table 11.
7
CAL
Setting this bit high initiates an internal offset calibration. When the calibration is completed, this pin can be reset low,
and the internal offset that is stored in the on-chip offset registers is automatically removed from the ADCs results.
6 to 4
PD2 to PD0
Power-down bits. These bits select which power-down mode is programmed. See Table 7.
3 to 0
G3 to G0
Gain selection bits. These bits select which gain setting is used on the front-end PGA. See Table 6.
Table 10. Write Address Bits
WR3
WR2
WR1
WR0
Read Register Addressed
0
1
Control register
CS
SCLK
DOUTA
PD0/DIN
06732-
030
10
14
16
THREE-STATE
11
12
13
17
THREE-
STATE
15
DB12
DB13
18
20
19
32
33
DB0
THREE-STATE
WR1
WR0
RD3
RD2
RD1
RD0
CAL
PD2
PD1
PD0
G3
G2
G1
G0
WR2
WR3
t2
t8
t
QUIET
9
8
7
6
5
4
3
2
1
t13
t14
Figure 30. Timing Diagram for a Write Operation to the Control Register
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