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| 型号： | AD7298-1BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/25页 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT SPI/SRL 8CH 20LFCSP |
| 标准包装： | 1 |
| 位数： | 10 |
| 采样率（每秒）： | 1M |
| 数据接口： | DSP，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 23mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 20-LFCSP-WQ（4x4） |
| 包装： | 托盘 |
| 输入数目和类型： | 8 个单端，单极 |
AD7298-1
Rev. A | Page 15 of 24
CONTROL REGISTER
The control register of the AD7298-1 is a 16-bit, write-only
register. Data is loaded from the DIN pin of the AD7298-1 on
the falling edge of SCLK. The data is transferred on the DIN
line at the same time that the conversion result is read from the
part. The data transferred on the DIN line corresponds to the
AD7298-1 configuration for the next conversion. This requires
16 serial clocks for every data transfer. Only the information
provided on the first 16 falling clock edges (after the falling
edge of CS) is loaded to the control register. MSB denotes the
first bit in the data stream. The bit functions are outlined in
Table 6 and Table 7. At power-up, the default content of the
control register is all zeros.
Table 6. Control Register Bit Functions
MSB
LSB
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
WRITE
REPEAT
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
0
DONTC
EXT_REF
DONTC
PPD
Table 7. Control Register Bit Function Description
Bit
Mnemonic
Description
D15
WRITE
The value written to this bit determines whether the subsequent 15 bits are loaded to the control register. If this
bit is a 1, the following 15 bits are written to the control register. If this bit is a 0, then the remaining 15 bits are not
loaded to the control register, and it remains unchanged.
D14
REPEAT
This bit enables the repeated conversion of the selected sequence of channels.
D13 to
D6
CH0 to
CH7
These eight channel selection bits are loaded at the end of the current conversion and select which analog input
channel is to be converted in the next serial transfer, or they can select the sequence of channels for conversion in
the subsequent serial transfers. Each CHx bit corresponds to an analog input channel. A channel or sequence of
channels is selected for conversion by writing a 1 to the appropriate CHx bit/bits. Channel address bits
corresponding to the conversion result are output on DOUT prior to the 10 bits of data. The next channel to be
converted is selected by the mux on the 14th SCLK falling edge.
D5
0
Zero should be written to this bit.
D4, D3,
D1
DONTC
Don’t care.
D2
EXT_REF
Writing Logic 1 to this bit, enables the use of an external reference. The input voltage range for the external
reference is 1 V to 2.5 V. The external reference should not exceed 2.5 V or the device performance is affected.
D0
PPD
This partial power-down mode is selected by writing a 1 to this bit in the control register. In this mode, some of
the internal analog circuitry is powered down. The AD7298-1 retains the information in the control register while
in partial power-down mode. The part remains in this mode until a 0 is written to this bit.
Table 8. Channel Address Bits
ADD3
ADD2
ADD1
ADD0
Analog Input Channel
0
V
IN0
0
1
V
IN1
0
1
0
V
IN2
0
1
V
IN3
0
1
0
V
IN4
0
1
0
1
V
IN5
0
1
0
V
IN6
0
1
V
IN7
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