参数资料
型号: AD7304BRZ-REEL
厂商: Analog Devices Inc
文件页数: 18/20页
文件大小: 0K
描述: IC DAC 8BIT QUAD R-R 16-SOIC
产品培训模块: Data Converter Fundamentals
DAC Architectures
标准包装: 1,000
设置时间: 1µs
位数: 8
数据接口: 串行
转换器数目: 4
电压电源: 双 ±
功率耗散(最大): 60mW
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.295",7.50mm 宽)
供应商设备封装: 16-SOIC W
包装: 带卷 (TR)
输出数目和类型: 4 电压,单极;4 电压,双极
采样率(每秒): 1M
AD7304/AD7305
Rev. C | Page 7 of 20
Table 6. AD7305 Control Logic Truth Table
WR 1
A1
A0
LDAC2
Input Register Function
DAC Register Function
L
H
Register A loaded with DB0 to DB7
Latched with previous contents, no change
↑+
L
H
Register A latched with DB0 to DB7
Latched with previous contents, no change
L
H
Register B loaded with DB0 to DB7
Latched with previous contents, no change
↑+
L
H
Register B latched with DB0 to DB7
Latched with previous contents, no change
L
H
L
H
Register C loaded with DB0 to DB7
Latched with previous contents, no change
↑+
H
L
H
Register C latched with DB0 to DB7
Latched with previous contents, no change
L
H
Register D loaded with DB0 to DB7
Latched with previous contents, no change
↑+
H
Register D latched with DB0 to DB7
Latched with previous contents, no change
H
X
L
No effect
All input register contents loaded, register transparent
L
X
L
Input register x transparent to DB0 to DB7
Register transparent
H
X
↑+
No effect
All input register contents latched
H
X
H
No effect, device not selected
1
↑+ positive logic transition; ↓– negative logic transition; X don’t care.
2
LDAC is a level-sensitive input.
tAH
tDH
tLH
tLDW
tWR
tAS
tDS
tLS
tS
±1 LSB
ERROR BAND
A0, A1
WR
D0–D7
LDAC
VOUT
01114-006
Figure 6. AD7305 General Timing Diagram
tSDR
A0/SHDN
IDD
tSDN
01114-007
Figure 7. AD7305 Timing Diagram Zoom In
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