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参数资料
| 型号： | AD7306JR |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 通用总线功能 |
| 英文描述： | 5V High-Speed RS-232 Transceivers with 0.1uF Capacitors |
| 中文描述： | LINE TRANSCEIVER, PDSO24 |
| 封装： | SOIC-24 |
| 文件页数： | 4/8页 |
| 文件大小： | 149K |
| 代理商： | AD7306JR |
AD7306
–4–
REV. B
PIN FUNCT ION DE SCRIPT ION
SOIC
Pin
DIP
Pin
Mnemonic
Function
1
19
V+
Internally Generated Positive Supply (+9 V nominal). A 0.1
μ
F capacitor must be connected
between this pin and GND.
External Capacitor 1 T erminals. A 0.1
μ
F capacitor must be connected between these pins.
RS-232 Receiver R2 Input. T his input accepts RS-232 input voltages.
RS-232 T ransmitter (Driver) T 1 Output (T ypically
±
7.5 V).
RS-232 T ransmitter (Driver) T 2 Output (T ypically
±
7.5 V).
Power Supply Input (5 V
±
5%).
RS-422 Receiver R1, Differential Input B.
Receiver R1 Input. May be configured to accept either single ended RS-232 levels or
differential RS-422 levels. It is configured using the 232/
422
SEL pin.
RS-422 T ransmitter (Driver) T 3, Differential Output B.
RS-232 T ransmitter (Driver) T 3, Differential Output A.
No Connect Pins.
Ground Pin. Must be connected to 0 V.
Select Input. T his input configures Receiver R1 to accept either RS-232 or RS-422 signal lev-
els. A Logic 1 on this input selects 232 operation while a Logic 0 selects 422 operation.
T T L/CMOS Input to the RS-422 T ransmitter T 3.
T T L/CMOS Output from Receiver R1.
T T L/CMOS Input to RS-232 T ransmitter T 2.
T T L/CMOS Input to RS-232 T ransmitter T 1.
T T L/CMOS Output from Receiver R2.
External Capacitor 2 T erminals. A 0.1
μ
F capacitor must be connected between these pins.
Internally Generated Negative Supply (–9 V nominal). A 0.1
μ
F capacitor must be connected
between this pin and GND.
2, 3
4
5
6
7
8
9
20, 22
23
24
1
2
3
4
C1+, C1–
R2
IN
T 1
OUT
T 2
OUT
V
CC
R1
IN
(B)
R1
IN
/R1
IN
(A)
10
11
12, 13
14, 18
15
5
6
16, 21
7, 11
8
T 3
OUT
(B)
T 3
OUT
(A)
NC
GND
232/
422
SEL
16
17
19
20
21
22, 23
24
9
10
12
13
14
15, 17
18
T 3
IN
R1
OUT
T 2
IN
T 1
IN
R2
OUT
C2+, C2–
V–
PIN CONFIGURAT IONS
SOIC
V+
C1+
C1–
V–
C2–
C2+
GND
NC
NC
NC = NO CONNECT
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
16
15
14
13
20
19
18
17
AD7306
SOIC
TOP VIEW
(Not to Scale)
GND
R1
IN
/R1
IN
(A)
T2
OUT
T1
OUT
R2
IN
R1
IN
(B)
T3
OUT
(B)
R2
OUT
T3
IN
232/422 SEL
V
CC
R1
OUT
T1
IN
T2
IN
T3
OUT
(A)
DIP
R1
IN
/R1
IN
(A)
V+
C1+
C1–
V–
C2–
C2+
GND
NC
NC
T2
OUT
T1
OUT
R2
IN
R1
IN
(B)
T3
OUT
(B)
R2
OUT
T3
IN
232/422 SEL
V
CC
NC = NO CONNECT
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
16
15
14
13
20
19
18
17
AD7306
DIP
TOP VIEW
(Not to Scale)
GND
R1
OUT
T1
IN
T2
IN
T3
OUT
(A)
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