参数资料
型号: AD7322BRUZ
厂商: Analog Devices Inc
文件页数: 8/37页
文件大小: 0K
描述: IC ADC 12BIT+ SAR 2CHAN 14TSSOP
标准包装: 96
位数: 12
采样率(每秒): 1M
数据接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
功率耗散(最大): 30mW
电压电源: 双 ±
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 14-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 14-TSSOP
包装: 管件
输入数目和类型: 2 个单端,单极;2 个单端,双极;1 个差分,单极;1 个差分,双极
产品目录页面: 777 (CN2011-ZH PDF)
配用: EVAL-AD7322CBZ-ND - BOARD EVALUATION FOR AD7322
Data Sheet
AD7322
Rev. B | Page 15 of 36
THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7322 is a fast, 2-channel, 12-bit plus sign, bipolar input,
serial ADC. The AD7322 can accept bipolar input ranges that
include ±10 V, ±5 V, and ±2.5 V; it can also accept a 0 V to
+10 V unipolar input range. A different analog input range can
be programmed on each analog input channel via the on-chip
registers. The AD7322 has a high speed serial interface that can
operate at throughput rates up to 1 MSPS.
The AD7322 requires VDD and VSS dualsupplies for the high voltage
analog input structures. These supplies must be equal to or greater
than the analog input range. See Table 6 for the requirements of
these supplies for each analog input range. The AD7322 requires
a low voltage 2.7 V to 5.25 V VCC supply to power the ADC core.
Table 6. Reference and Supply Requirements
for Each Analog Input Range
Selected
Analog Input
Range (V)
Reference
Voltage (V)
Full-Scale
Input
Range (V)
VCC (V)
Minimum
VDD/VSS (V)1
±10
2.5
±10
3/5
±10
3.0
±12
3/5
±12
±5
2.5
±5
3/5
±5
3.0
±6
3/5
±6
±2.5
2.5
±2.5
3/5
±5
3.0
±3
3/5
±5
0 to +10
2.5
0 to +10
3/5
+10/AGND
3.0
0 to +12
3/5
+12/AGND
1
Guaranteed performance for VDD = 12 V to 16.5 V and VSS = 12 V to 16.5 V.
The performance specifications are guaranteed for VDD = 12 V
to 16.5 V and VSS = 12 V to 16.5 V. With VDD and VSS supplies
outside this range, the AD7322 is fully functional but performance
is not guaranteed. When the AD7322 is configured with the
minimum VDD and VSS supplies for a chosen analog input range,
the throughput rate should be decreased from the maximum
throughput range (see the Typical Performance Characteristics
section). Figure 18 and Figure 19 show the change in INL and
DNL as the VDD and VSS voltages are varied. When operating at
the maximum throughput rate, as the VDD and VSS supply voltages
are reduced, the INL and DNL error increases. However, as the
throughput rate is reduced with the minimum VDD and VSS
supplies, the INL and DNL error is reduced.
Figure 31 shows the change in THD as the VDD and VSS supplies
are reduced. At the maximum throughput rate, the THD degrades
significantly as VDD and VSS are reduced. It is therefore necessary
to reduce the throughput rate when using minimum VDD and
VSS supplies so that there is less degradation of THD and the
specified performance can be maintained. The degradation is
due to an increase in the on resistance of the input multiplexer
when the VDD and VSS supplies are reduced.
The analog inputs can be configured as two single-ended inputs,
one true differential input, or one pseudo differential input.
Selection can be made by programming the mode bits, Mode 0
and Mode 1, in the control register.
The serial clock input accesses data from the part and provides
the clock source for the successive approximation ADC. The
AD7322 has an on-chip 2.5 V reference. However, the AD7322
can also work with an external reference. On power-up, the exter-
nal reference operation is the default option. If the internal
reference is the preferred option, the user must write to the
reference bit in the control register to select the internal refer-
ence operation.
The AD7322 also features power-down options to allow power
saving between conversions. The power-down modes are selected
by programming the on-chip control register as described in the
CONVERTER OPERATION
The AD7322 is a successive approximation ADC built around
two capacitive DACs. Figure 23 and Figure 24 show simplified
schematics of the ADC in single-ended mode during the
acquisition and conversion phases, respectively. Figure 25 and
Figure 26 show simplified schematics of the ADC in differential
mode during acquisition and conversion phase, respectively.
The ADC is composed of control logic, a SAR, and capacitive
DACs. In Figure 23 (the acquisition phase), SW2 is closed and
SW1 is in Position A, the comparator is held in a balanced
condition, and the sampling capacitor array acquires the signal
on the input.
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
AGND
SW2
SW1
A
B
CS
VIN0
04863-
017
Figure 23. ADC Acquisition Phase (Single-Ended)
When the ADC starts a conversion (see Figure 24), SW2 opens
and SW1 moves to Position B, causing the comparator to become
unbalanced. The control logic and the charge redistribution
DAC are used to add and subtract fixed amounts of charge from
the capacitive DAC to bring the comparator back into a balanced
condition. When the comparator is rebalanced, the conversion
is complete. The control logic generates the ADC output code.
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
AGND
SW2
SW1
A
B
CS
VIN0
04863-
018
Figure 24. ADC Conversion Phase (Single-Ended)
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