参数资料
型号: AD736JRZ-R7
厂商: Analog Devices Inc
文件页数: 11/20页
文件大小: 0K
描述: IC TRUE RMS/DC CONV LP 8-SOIC TR
产品培训模块: Introduction to Analog RMS-to-DC Technology: Converters and Applications
标准包装: 1,000
电流 - 电源: 160µA
电源电压: 2.8V,-3.2V ~ ±16.5V
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SO
包装: 带卷 (TR)
配用: AD736-EVALZ-ND - BOARD EVALUATION FOR AD736
Data Sheet
Mathematically, the rms value of a voltage is defined (using a
simplified equation) as
V rms = Avg ( V 2 )
This involves squaring the signal, taking the average, and
then obtaining the square root. True rms converters are smart
rectifiers; they provide an accurate rms reading regardless of the
type of waveform being measured. However, average responding
converters can exhibit very high errors when their input signals
deviate from their precalibrated waveform; the magnitude of
the error depends on the type of waveform being measured. For
example, if an average responding converter is calibrated to
measure the rms value of sine wave voltages and then is used to
measure either symmetrical square waves or dc voltages, the
converter has a computational error 11% (of reading) higher
than the true rms value (see Table 5).
CALCULATING SETTLING TIME USING FIGURE 16
Figure 16 can be used to closely approximate the time required
for the AD736 to settle when its input level is reduced in amplitude.
The net time required for the rms converter to settle is the
difference between two times extracted from the graph (the
initial time minus the final settling time). As an example, consider
the following conditions: a 33 μF averaging capacitor, a 100 mV
initial rms input level, and a final (reduced) 1 mV input level.
AD736
The settling time corresponding to the new or final input level
of 1 mV is approximately 8 seconds. Therefore, the net time for
the circuit to settle to its new value is 8 seconds minus 80 ms,
which is 7.92 seconds. Note that because of the smooth decay
characteristic inherent with a capacitor/diode combination, this
is the total settling time to the final value (that is, not the settling
time to 1%, 0.1%, and so on, of the final value). In addition, this
graph provides the worst-case settling time because the AD736
settles very quickly with increasing input levels.
RMS MEASUREMENT—CHOOSING THE OPTIMUM
VALUE FOR C AV
Because the external averaging capacitor, C AV , holds the
rectified input signal during rms computation, its value directly
affects the accuracy of the rms measurement, especially at low
frequencies. Furthermore, because the averaging capacitor
appears across a diode in the rms core, the averaging time
constant increases exponentially as the input signal is reduced.
This means that as the input level decreases, errors due to
nonideal averaging decrease, and the time required for the
circuit to settle to the new rms level increases. Therefore, lower
input levels allow the circuit to perform better (due to increased
averaging) but increase the waiting time between measurements.
Obviously, when selecting C AV , a trade-off between computational
accuracy and settling time is required.
From Figure 16, the initial settling time (where the 100 mV line
intersects the 33 μF line) is approximately 80 ms.
Table 5. Error Introduced by an Average Responding Circuit whe n Measuring Common Waveforms
Waveform Type 1 V Peak Amplitude
Undistorted Sine Wave
Symmetrical Square Wave
Undistorted Triangle Wave
Gaussian Noise (98% of Peaks <1 V)
Rectangular
Pulse Train
Crest Factor
(V PEAK /V rms)
1.414
1.00
1.73
3
2
10
True RMS
Value (V)
0.707
1.00
0.577
0.333
0.5
0.1
Average Responding Circuit
Calibrated to Read RMS Value of
Sine Waves (V)
0.707
1.11
0.555
0.295
0.278
0.011
% of Reading Error Using
Average Responding Circuit
0
+11.0
?3.8
?11.4
?44
?89
SCR Waveforms
50% Duty Cycle
25% Duty Cycle
2
4.7
0.495
0.212
0.354
0.150
?28
?30
Rev. I | Page 11 of 20
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