参数资料
| 型号： | AD7376ARWZ100 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 6/20页 |
| 文件大小： | 0K |
| 描述： | IC DIGITAL POT 100K 16-SOIC |
| 标准包装： | 47 |
| 接片： | 128 |
| 电阻（欧姆）： | 100k |
| 电路数： | 1 |
| 温度系数： | 标准值 300 ppm/°C |
| 存储器类型： | 易失 |
| 接口： | 4 线 SPI（芯片选择） |
| 电源电压： | 4.5 V ~ 33 V，±4.5 V ~ 16.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC W |
| 包装： | 管件 |
| 产品目录页面： | 787 (CN2011-ZH PDF) |
| 配用： | EVAL-AD7376EBZ-ND - BOARD EVAL FOR AD7376 |
AD7376
Rev. D | Page 14 of 20
DAISY-CHAIN OPERATION
0
11
19-
027
CS
SDI
SERIAL
REGISTER
D
CK
Q
RS
SHDN
SDO
RS
CLK
Figure 27. Detailed SDO Output Schematic of the AD7376
Figure 27 shows the details of the serial data output pin (SDO).
SDO shifts out the SDI content in the previous frame; therefore,
it can be used for daisy-chaining multiple devices. The SDO pin
contains an open-drain N-Channel MOSFET and requires a
pull-up resistor if the SDO function is used.
Users need to tie the SDO pin of one package to the SDI pin of
the next package. For example, in Figure 28, if two AD7376s are
daisy-chained, a total of 14 bits of data are required for each
operation. The first set of seven bits goes to U2; the second set
of seven bits goes to U1. CS should be kept low until all 14 bits
are clocked into their respective serial registers. Then CS is
pulled high to complete the operation.
When daisy-chaining multiple devices, users may need to
increase the clock period because the pull-up resistor and the
capacitive loading at the SDO to SDI interface may induce a
time delay to subsequent devices.
AD7376
SDO
SDI
CLK
CS
AD7376
SDO
SDI
CLK
CS
C
5V
RPU
2.2kΩ
MOSI
SS
SCLK
0
11
19-
028
U1
U2
Figure 28. Daisy-Chain Configuration
ESD PROTECTION
All digital inputs are protected with a series input resistor and
an ESD structure shown in Figure 29. These structures apply to
digital input pins CS, CLK, SDI, RS, and SHDN.
INPUT
340Ω
LOGIC
PINS
VDD
GND
0
11
19-
029
Figure 29. Equivalent ESD Protection Circuit
All analog terminals are also protected by ESD protection
diodes, as shown in Figure 30.
VSS
VDD
A
W
B
0
11
19-
030
Figure 30. Equivalent ESD Protection Analog Pins
TERMINAL VOLTAGE OPERATING RANGE
The AD7376 VDD and VSS power supplies define the boundary
conditions for proper 3-terminal digital potentiometer oper-
ation. Applied signals present on Terminals A, B, and W that
are more positive than VDD or more negative than VSS will be
clamped by the internal forward-biased diodes (see Figure 30).
POWER-UP AND POWER-DOWN SEQUENCES
Because of the ESD protection diodes that limit the voltage
compliance at Terminals A, B, and W (see Figure 30), it is
important to power VDD/VSS before applying voltage to
Terminals A, B, and W. Otherwise, the diodes are forward
biased such that VDD/VSS are powered unintentionally and affect
the system. Similarly, VDD/VSS should be powered down last.
The ideal power-up sequence is in the following order: GND,
VDD, VSS, digital inputs, and VA/VB/VW. The order of powering
VA, VB, VW, and the digital inputs is not important, as long as
they are powered after VDD/VSS.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD7376ARWZ10-RL | 功能描述:IC POT DIGITAL 10K 16-SOIC RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数字电位器 系列:- 标准包装:3,000 系列:DPP 接片:32 电阻（欧姆）:10k 电路数:1 温度系数:标准值 300 ppm/°C 存储器类型:非易失 接口:3 线串行（芯片选择，递增，增/减） 电源电压:2.5 V ~ 6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-WFDFN 裸露焊盘 供应商设备封装:8-TDFN（2x3） 包装:带卷 (TR) |
| AD7376ARWZ50 | 功能描述:IC DIGITAL POT 50K 16-SOIC RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数字电位器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 接片:256 电阻（欧姆）:100k 电路数:1 温度系数:标准值 35 ppm/°C 存储器类型:非易失 接口:3 线串口 电源电压:2.7 V ~ 5.25 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-WDFN 裸露焊盘 供应商设备封装:8-TDFN-EP（3x3） 包装:剪切带 (CT) 产品目录页面:1399 (CN2011-ZH PDF) 其它名称:MAX5423ETA+TCT |
| AD7376EVAL | 制造商:Analog Devices 功能描述: |
| ad7376xruz100 | 制造商:Analog Devices 功能描述:+/-15V DIGITAL POTENTIOMETERS 10K OHM - Bulk |
| AD7376XRUZ100-R7 | 制造商:Analog Devices 功能描述:+/-15V DIGITAL POTENTIOMETERS 10K OHM - Tape and Reel |
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