参数资料
型号: AD7392AR
厂商: Analog Devices Inc
文件页数: 6/20页
文件大小: 0K
描述: IC DAC 12BIT PARALLEL 3V 20-SOIC
产品培训模块: Data Converter Fundamentals
DAC Architectures
标准包装: 37
设置时间: 60µs
位数: 12
数据接口: 并联
转换器数目: 1
电压电源: 单电源
功率耗散(最大): 500µW
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-SOIC(0.295",7.50mm 宽)
供应商设备封装: 20-SOIC W
包装: 管件
输出数目和类型: 1 电压,单极;1 电压,双极
采样率(每秒): 17k
AD7392/AD7393
Rev. C | Page 14 of 20
RESET PIN (RS)
Forcing the asynchronous RS pin low sets the DAC register to
all 0s, so the DAC output voltage is 0 V. The reset function is
useful for setting the DAC outputs to 0 at power-up or after a
power supply interruption. Test systems and motor controllers
are two of many applications that benefit from powering up to a
known state. The external reset pulse can be generated by three
methods:
The microprocessor’s power-on RESET signal
An output from the microprocessor
An external resistor and capacitor
RESET has a Schmitt-trigger input, which results in a clean
reset function when using external resistor-/capacitor-generated
pulses (see Table 6).
POWER SHUTDOWN (SHDN)
Maximum power savings can be achieved by using the power
shutdown control function. This hardware-activated feature is
controlled by the active low input SHDN pin. This pin has a
Schmitt-trigger input that helps desensitize it to slowly changing
inputs. Setting this pin to logic low reduces the internal con-
sumption of the AD7392/AD7393 to nanoamp levels, guaranteed
to 1.5 μA maximum over the operating temperature range. If
power is present at all times on the VDD pin while in shutdown
mode, the internal DAC register retains the last programmed
data value. The digital interface is still active in shutdown so
that code changes can be made that produce new DAC settings
when the device is taken out of shutdown. This data is used
when the part is returned to the normal active state by placing
the DAC back to its programmed voltage setting. Figure 23
shows a plot of shutdown recovery time with both IDD and VOUT
displayed. In the shutdown state, the DAC output amplifier
exhibits an open-circuit high resistance state. Any load that is
connected stabilizes at its termination voltage. If the power
shutdown feature is not needed, the user should tie the SHDN
pin to the VDD voltage to disable this function.
UNIPOLAR OUTPUT OPERATION
This is the basic mode of operation for the AD7392. The
AD7392 is designed to drive loads as low as 5 kΩ in parallel
with 100 pF (see Figure 32). The code table for this operation is
shown in Table 7.
The circuit can be configured with an external reference
plus power supply or powered from a single dedicated regu-
lator or reference depending on the application performance
requirements.
0
112
1-
0
32
1
20
19
17, 18
2.7V TO 5.5V
VDD
GND
AD7392
VOUT
VREF
R
RL
≥5k
CL
≥100pF
0.1F
0.01F
10F
NOTES
1. DIGITAL INTERFACE CIRCUITRY OMITTED FOR CLARITY
EXT
REF
Figure 32. AD7392 Unipolar Output Operation
Table 7. Unipolar Code Table
DAC Register No.
Hexadecimal
Decimal
Output Voltage (V), VREF = 2.5 V
0xFFF
4095
2.4994
0x801
2049
1.2506
0x800
2048
1.2500
0x7FF
2047
1.2494
0x000
0
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