参数资料
型号: AD7475BRMZ
厂商: Analog Devices Inc
文件页数: 24/25页
文件大小: 0K
描述: IC ADC 12BIT SERIAL LP 8MSOP
标准包装: 50
位数: 12
采样率(每秒): 1M
数据接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
功率耗散(最大): 10.5mW
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP,8-MSOP(0.118",3.00mm 宽)
供应商设备封装: 8-MSOP
包装: 管件
输入数目和类型: 1 个单端,单极
AD7475/AD7495
Rev. B | Page 7 of 24
TIMING SPECIFICATIONS1
VDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, REF IN = 2.5 V (AD7475), TA = TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Limit at TMIN, TMAX
Unit
Description
fSCLK2
10
kHz min
20
MHz max
tCONVERT
16 × tSCLK
tSCLK = 1/fSCLK
800
ns max
fSCLK = 20 MHz
tQUIET
100
ns min
Minimum quiet time required between conversions
t2
10
ns min
CS to SCLK setup time
t33
22
ns max
Delay from CS until SDATA three-state disabled
t4
40
ns max
Data access time after SCLK falling edge
t5
0.4 tSCLK
ns min
SCLK low pulse width
t6
0.4 tSCLK
ns min
SCLK high pulse width
t7
10
ns min
SCLK to data valid hold time
t84
10
ns min
SCLK falling edge to SDATA high impedance
45
ns max
SCLK falling edge to SDATA high impedance
t9
20
ns max
CS rising edge to SDATA high impedance
tPOWER-UP
20
μs max
Power-up time from full power-down (AD7475)
650
μs max
Power-up time from full power-down (AD7495)
1 Guaranteed by initial characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
2 Mark/space ratio for the SCLK input is 40/60 to 60/40.
3 Measured with the load circuit of Figure 4 and defined as the time required for the output to cross 0.8 V or 2.0 V.
4 t8 and t9 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 4. The measured number is
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times, t8 and t9, quoted in the timing characteristics are
the true bus relinquish times of the part and are independent of the bus loading.
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