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参数资料
| 型号： | AD7477AAKSZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/29页 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 1MSPS LP SC70-6 |
| 标准包装： | 10,000 |
| 位数： | 10 |
| 采样率（每秒）： | 1M |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 17.5mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 6-TSSOP，SC-88，SOT-363 |
| 供应商设备封装： | SC-70-6 |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个单端，单极 |
| 配用： | EVAL-AD7477CBZ-ND - BOARD EVALUATION FOR AD7477 |
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AD7476A/AD7477A/AD7478A
Rev. F | Page 21 of 28
SERIAL INTERFACE
Figure 24, Figure 25, and Figure 26 show the detailed timing
diagrams for serial interfacing to the AD7476A, AD7477A, and
AD7478A, respectively. The serial clock provides the conversion
clock and also controls the transfer of information from the
AD7476A/AD7477A/AD7478A during conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode
and takes the bus out of three-state; the analog input is sampled
at this point. Also, the conversion is initiated at this point.
For the AD7476A, the conversion requires 16 SCLK cycles to
complete. Once 13 SCLK falling edges have elapsed, the track-
and-hold goes back into track on the next SCLK rising edge, as
shown in Figure 24 at Point B. On the 16th SCLK falling edge,
the SDATA line goes back into three-state. If the rising edge of
CS occurs before 16 SCLKs have elapsed, the conversion is
terminated and the SDATA line goes back into three-state;
otherwise, SDATA returns to three-state on the 16th SCLK
falling edge, as shown in Figure 24. Sixteen serial clock cycles
are required to perform the conversion process and to access
data from the AD7476A.
For the AD7477A, the conversion requires 14 SCLK cycles to
complete. Once 13 SCLK falling edges have elapsed, the track-
and-hold goes back into track on the next rising edge as shown
at Point B in Figure 25. If the rising edge of CS occurs before
14 SCLKs have elapsed, the conversion is terminated and the
SDATA line goes back into three-state. If 16 SCLKs are
considered in the cycle, SDATA returns to three-state on the
16th SCLK falling edge, as shown in Figure 25.
For the AD7478A, the conversion requires 12 SCLK cycles to
complete. The track-and-hold goes back into track on the rising
edge after the 11th falling edge, as shown in Figure 26 at Point B. If
the rising edge of CS occurs before 12 SCLKs have elapsed, the
conversion is terminated and the SDATA line goes back into three-
state. If 16 SCLKs are considered in the cycle, SDATA returns to
three-state on the 16th SCLK falling edge, as shown in Figure 26.
CS
SCLK
SDATA
t2
t6
t3
t4
t7
t5
t8
tCONVERT
tQUIET
ZERO
DB11
DB10
DB2
DB1
DB0
B
THREE-STATE
THREE-
STATE
Z
4 LEADING ZEROS
1
3
13
14
15
16
t1
1/THROUGHPUT
24
5
02930-024
Figure 24. AD7476A Serial Interface Timing Diagram
SCLK
1
5
13
15
THREE-STATE
t4
2
16
t5
t3
t2
DB9
DB8
DB0
ZERO
t6
t7
t8
14
4 LEADING ZEROS
ZERO
Z
t1
1/ THROUGHPUT
ZERO
2 TRAILING ZEROS
SDATA
tCONVERT
tQUIET
B
THREE-STATE
CS
4
02930-
025
3
Figure 25. AD7477A Serial Interface Timing Diagram
CS
SCLK
1
13
15
SDATA
4 LEADING ZEROS
THREE-STATE
t4
2
3
16
t5
t3
t2
THREE-STATE
DB7
t6
t7
t8
14
ZERO
Z
t1
1/ THROUGHPUT
ZERO
11
12
4 TRAILING ZEROS
tCONVERT
tQUIET
B
4
029
30
-02
6
Figure 26. AD7478A Serial Interface Timing Diagram
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相关代理商/技术参数 |
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|---|---|
| AD7477AAKSZ-REEL3 | 制造商:AD 制造商全称:Analog Devices 功能描述:2.35 V to 5.25 V, 1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SC70 |
| AD7477AAKSZ-REEL7 | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 10-bit Serial 6-Pin SC-70 T/R |
| AD7477AAKSZ-REEL73 | 制造商:AD 制造商全称:Analog Devices 功能描述:2.35 V to 5.25 V, 1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SC70 |
| AD7477AARM | 制造商:Rochester Electronics LLC 功能描述:10-BIT LOW POWER ADC IN USOIC PKG I.C - Bulk 制造商:Analog Devices 功能描述:IC 10BIT ADC SMD 7477 MSOP8 |
| AD7477AARM-REEL | 制造商:Analog Devices 功能描述:ADC SGL SAR 1MSPS 10-BIT SERL 8MSOP - Tape and Reel 制造商:Rochester Electronics LLC 功能描述:10-BIT LOW POWER ADC IN USOIC PKG I.C - Tape and Reel |
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