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参数资料
| 型号： | AD7477ARTZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 9/25页 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 1MSPS SOT23-6 |
| 标准包装： | 3,000 |
| 位数： | 10 |
| 采样率（每秒）： | 1M |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 17.5mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SOT-23-6 |
| 供应商设备封装： | SOT-23-6 |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个单端，单极 |
| 配用： | EVAL-AD7477CBZ-ND - BOARD EVALUATION FOR AD7477 |
AD7476/AD7477/AD7478
Rev. F | Page 16 of 24
To exit this mode of operation and power up the AD7476/
AD7477/AD7478 again, perform a dummy conversion. On the
falling edge of CS, the device begins to power up, and continues
to power up as long as CS is held low until after the falling edge
of the tenth SCLK. The device is fully powered up once 16
SCLKs have elapsed and, as shown in
, valid data
results from the next conversion. If
CS is brought high before
the tenth falling edge of SCLK, the AD7476/AD7477/AD7478
again goes back into power-down. This avoids accidental
power-up due to glitches on the CS line or an inadvertent burst
of eight SCLK cycles while CS is low. Although the device may
begin to power up on the falling edge of CS, it powers down
again on the rising edge of CS as long as it occurs before the
tenth SCLK falling edge.
Power-Down Mode
This mode is intended for use in applications where slower
throughput rates are required; either the ADC is powered
between each conversion, or a series of conversions can be
performed at a high throughput rate and the ADC is then
powered down for a relatively long duration between these
bursts of several conversions. When the AD7476/AD7477/
AD7478 is in power-down mode, all analog circuitry is
powered down.
To enter power-down, the conversion process must be
interrupted by bringing CS high any time after the second
falling edge of SCLK and before the tenth falling edge of SCLK,
as shown in
. Once
CS is brought high in this window
of SCLKs, the part enters power-down and the conversion
initiated by the falling edge of CS is terminated and SDATA
goes back into three-state.
If CS is brought high before the second SCLK falling edge, the
part remains in normal mode and does not power down. This
avoids accidental power-down due to glitches on the CS line.
4 LEADING ZEROS + CONVERSION RESULT
CS
SCLK
SDATA
1
10
16
01
02
4-
01
9
Figure 19. Normal Mode Operation
110
16
2
THREE-STATE
CS
SCLK
SDATA
01
02
4-
02
0
Figure 20. Entering Power-Down Mode
16
10
1
16
1
A
CS
SCLK
SDATA
INVALID DATA
VALID DATA
THE PART BEGINS
TO POWER UP
THE PART IS FULLY POWERED
UP WITH VIN FULLY ACQUIRED
01
02
4-
0
21
Figure 21. Exiting Power-Down Mode
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD7477ARTZ-REEL73 | 制造商:AD 制造商全称:Analog Devices 功能描述:1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23 |
| AD7477AWARMZ | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 10-bit Serial 8-Pin MSOP T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 1MSPS 10-BIT SERL 8MSOP - Rail/Tube |
| AD7477AWARMZ-RL | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 10-bit Serial 8-Pin MSOP T/R 制造商:Analog Devices 功能描述:10-BIT LOW POWER ADC IN USOIC PKG I.C - Tape and Reel |
| AD7477SRT | 制造商:AD 制造商全称:Analog Devices 功能描述:1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23 |
| AD7477SRT-500RL7 | 制造商:AD 制造商全称:Analog Devices 功能描述:1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23 |
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