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参数资料
| 型号： | AD7477ARTZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 11/25页 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 1MSPS SOT23-6 |
| 标准包装： | 10,000 |
| 位数： | 10 |
| 采样率（每秒）： | 1M |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 17.5mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SOT-23-6 |
| 供应商设备封装： | SOT-23-6 |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个单端，单极 |
| 配用： | EVAL-AD7477CBZ-ND - BOARD EVALUATION FOR AD7477 |
AD7476/AD7477/AD7478
Rev. F | Page 18 of 24
SERIAL INTERFACE
Sixteen serial clock cycles are required to perform the
conversion process and to access data from the AD7476/
AD7477/AD7478.
diagrams for serial interfacing to the AD7476, AD7477, and
AD7478, respectively. The serial clock provides the conversion
clock and controls the transfer of information from the part
during conversion.
CS going low provides the first leading zero to be read by the
microcontroller or DSP. The remaining data is then clocked out
by subsequent SCLK falling edges, beginning with the second
leading zero. Thus, the first falling clock edge on the serial clock
has the first leading zero provided and also clocks out the
second leading zero. The final bit in the data transfer is valid on
the 16th falling edge, having clocked out on the previous (15th)
falling edge. In applications with a slower SCLK, it is possible to
read data on each SCLK rising edge, although the first leading
zero has to be read on the first SCLK falling edge after the CS
falling edge. Therefore, the first rising edge of SCLK after the
CS falling edge provides the second leading zero. The 15th
rising SCLK edge has DB0 provided or the final zero for the
AD7477 and AD7478. This may not work with most
microcontrollers/DSPs, but could possibly be used with FPGAs
and ASICs.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode,
takes the bus out of three-state, and samples the analog input at
this point. The conversion initiates and requires 16 SCLK cycles
to complete. Once 13 SCLK falling edges have elapsed, the
track-and-hold goes back into track on the next SCLK rising
edge as shown at Point B in
, and
.
On the sixteenth SCLK falling edge, the SDATA line will go
back into three-state. If the rising edge of
CS occurs before
16 SCLKs have elapsed, the conversion terminates and the
SDATA line goes back into three-state; otherwise, SDATA
returns to three-state on the 16th SCLK falling edge as shown in
,
, and
SCLK
SDATA
CS
12345
13
14
15
16
B
THREE-STATE
THREE-
STATE
Z
ZERO
DB11
DB10
DB2
DB1
DB0
t1
t2
t3
t4
t7
t5
t6
t8
tQUIET
tCONVERT
4 LEADING ZEROS
0
1024-
023
Figure 23. AD7476 Serial Interface Timing Diagram
SCLK
SDATA
CS
1234
5
13
14
15
16
B
THREE-STATE
THREE-
STATE
Z
ZERO
DB9
DB8
DB0
ZERO
t1
t2
t3
t4
t7
t5
t6
t8
tQUIET
tCONVERT
4 LEADING ZEROS
2 TRAILING ZEROS
0
10
24-
024
Figure 24. AD7477 Serial Interface Timing Diagram
SCLK
SDATA
CS
1234
12
13
14
15
16
B
THREE-STATE
THREE-
STATE
Z
ZERO
DB7
ZERO
t1
t2
t3
t4
t7
t5
t6
t8
tQUIET
tCONVERT
4 LEADING ZEROS
4 TRAILING ZEROS
8 BITS OF DATA
0
10
24-
02
5
Figure 25. AD7478 Serial Interface Timing Diagram
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD7477ARTZ-REEL3 | 制造商:AD 制造商全称:Analog Devices 功能描述:1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23 |
| AD7477ARTZ-REEL7 | 功能描述:IC ADC 10BIT 1MSPS SOT23-6 RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:2,500 系列:- 位数:16 采样率（每秒）:15 数据接口:MICROWIRE?，串行，SPI? 转换器数目:1 功率耗散（最大）:480µW 电压电源:单电源 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:38-WFQFN 裸露焊盘 供应商设备封装:38-QFN（5x7） 包装:带卷 (TR) 输入数目和类型:16 个单端，双极；8 个差分，双极 配用:DC1011A-C-ND - BOARD DELTA SIGMA ADC LTC2494 |
| AD7477ARTZ-REEL73 | 制造商:AD 制造商全称:Analog Devices 功能描述:1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23 |
| AD7477AWARMZ | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 10-bit Serial 8-Pin MSOP T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 1MSPS 10-BIT SERL 8MSOP - Rail/Tube |
| AD7477AWARMZ-RL | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 10-bit Serial 8-Pin MSOP T/R 制造商:Analog Devices 功能描述:10-BIT LOW POWER ADC IN USOIC PKG I.C - Tape and Reel |
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