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| 型号： | AD7478WARTZ-RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 25/25页 |
| 文件大小： | 0K |
| 描述： | IC ADC 8BIT 1MSPS SOT23-6 |
| 标准包装： | 1 |
| 位数： | 8 |
| 采样率（每秒）： | 1M |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 17.5mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SOT-23-6 |
| 供应商设备封装： | SOT-23-6 |
| 包装： | 标准包装 |
| 输入数目和类型： | 1 个单端，单极 |
| 产品目录页面： | 778 (CN2011-ZH PDF) |
| 其它名称： | AD7478WARTZ-RL7DKR |
AD7476/AD7477/AD7478
Rev. F | Page 8 of 24
Parameter
Unit
Test Conditions/Comments
Power Dissipation5
Normal Mode (Operational)
17.5
mW max
VDD = 5 V, fSAMPLE = 1 MSPS
4.8
mW max
VDD = 3 V, fSAMPLE = 1 MSPS
Full Power-Down
5
μW max
VDD = 5 V, SCLK off
1 Temperature range for A version is 40°C to +85°C; temperature range for S version is 55°C to +125°C.
2 Operational from VDD = 2.0 V, with input high voltage, VINH = 1.8 V minimum.
4 Guaranteed by characterization.
TIMING SPECIFICATIONS
VDD = 2.35 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.
Table 4.
3 V
5 V
Unit
Description
fSCLK4
10
kHz min
20
MHz
max
A version
12
MHz
max
B version
tCONVERT
16 × tSCLK
tQUIET
50
ns min
Minimum quiet time required between bus relinquish and start of next conversion
t1
10
ns min
Minimum CS pulsewidth
t2
10
ns min
CS to SCLK setup time
t35
20
ns max
Delay from CS until SDATA three-state disabled
t45
40
20
ns max
Data access time after SCLK falling edge, A version
70
20
ns max
Data access time after SCLK falling edge, B version
t5
0.4 ×
tSCLK
0.4 ×
tSCLK
ns min
SCLK low pulsewidth
t6
0.4 ×
tSCLK
0.4 ×
tSCLK
ns min
SCLK high pulsewidth
t7
10
ns min
SCLK to data valid hold time
t86
10
ns min
SCLK falling edge to SDATA high impedance
25
ns max
SCLK falling edge to SDATA high impedance
tPOWER-UP7
1
μs typ
Power-up time from full power-down
1 3 V specifications apply from VDD = 2.7 V to 3.6 V for A version; 3 V specifications apply from VDD = 2.35 V to 3.6 V for B version; 5 V specifications apply from
VDD = 4.75 V to 5.25 V.
2 Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
3 Version A timing specifications apply to the AD7477 and AD7478 S version; B version timing specifications apply to the AD7476 S version.
4 Mark/space ratio for the SCLK input is 40/60 to 60/40.
5 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.
6 t8 is derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated to
remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, is the true bus relinquish time of the part and is independent of the bus
loading.
01
02
4-
00
2
200A
IOL
200A
IOH
1.6V
TO OUTPUT
PIN
CL
50pF
Figure 2. Load Circuit for Digital Output Timing Specifications
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| AD7478WARTZ-RL734 | 制造商:AD 制造商全称:Analog Devices 功能描述:1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23 |
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