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| 型号： | AD7490BRU-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 26/29页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 16CH 28-TSSOP T/R |
| 产品变化通告： | IDD Specification Change 17/Jun/2009 Product Discontinuance 27/Oct/2011 |
| 标准包装： | 2,500 |
| 位数： | 12 |
| 采样率（每秒）： | 1M |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 12.5mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 28-TSSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 16 个单端，单极 |
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Data Sheet
AD7490
Rev. D | Page 5 of 28
TIMING SPECIFICATIONS
VDD = 2.7 V to 5.25 V, VDRIVE ≤ VDD, REFIN = 2.5 V; TA = TMIN to TMAX, unless otherwise noted.
Table 2. Timing Specifications1
Limit at TMIN, TMAX
Parameter
VDD = 3 V
VDD = 5 V
Unit
Description
fSCLK2
10
kHz min
16
20
MHz max
tCONVERT
16 × tSCLK
tQUIET
50
ns min
Minimum quiet time required between bus relinquish and start of next conversion
t2
12
10
ns min
CS to SCLK setup time
20
14
ns max
Delay from CS until DOUT three-state disabled
t3b4
30
20
ns max
Delay from CS to DOUT valid
t43
60
40
ns max
Data access time after SCLK falling edge
t5
0.4 × tSCLK
ns min
SCLK low pulse width
t6
0.4 × tSCLK
ns min
SCLK high pulse width
t7
15
ns min
SCLK to DOUT valid hold time
15/50
ns min/max
SCLK falling edge to DOUT high impedance
t9
20
ns min
DIN setup time prior to SCLK falling edge
t10
5
ns min
DIN hold time after SCLK falling edge
t11
20
ns min
16th SCLK falling edge to CS high
t12
1
s max
Power-up time from full power-down/auto shutdown/auto standby modes
1
Guaranteed by characterization. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V (see Figure 2). The 3 V
operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.
2
The mark/space ratio for the SCLK input is 40/60 to 60/40. The maximum SCLK frequency is 16 MHz with VDD = 3 V to give a throughput of 870 kSPS. Care must be
taken when interfacing to account for data access time, t4, and the setup time required for the user’s processor. These two times determine the maximum SCLK
frequency with which the user’s system can operate (see the Serial Interface section).
3
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 0.7 VDRIVE .
4
t3b represents a worst-case figure for having ADD3 available on the DOUT line, that is, if the AD7490 goes back into three-state at the end of a conversion and some
other device takes control of the bus between conversions, the user has to wait a maximum time of t3b before having ADD3 valid on the DOUT line. If the DOUT line is
weakly driven to ADD3 between conversions, the user typically has to wait 17 ns at 3 V and 12 ns at 5 V after the CS falling edge before seeing ADD3 valid on DOUT.
5
t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the timing characteristics, is the true bus relinquish
time of the part and is independent of the bus loading.
02691-
002
200A
IOL
200A
IOH
1.6V
TO OUTPUT
PIN
CL
25pF
Figure 2. Load Circuit for Digital Output Timing Specifications
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