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| 型号： | AD7492BR-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 23/24页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT W/REF W/CLK 24-SOIC |
| 标准包装： | 1,000 |
| 位数： | 12 |
| 采样率（每秒）： | 1M |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 16.5mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 24-SOIC W |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个单端，单极 |
| 配用： | EVAL-AD7492CBZ-ND - BOARD EVALUATION FOR AD7492 |
AD7492
Rev. A | Page 8 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AD7492
TOP VIEW
(Not to Scale)
DB9
DB10
(MSB) DB11
AVDD
BUSY
PS/FS
REF OUT
CONVST
RD
AGND
CS
VIN
DB8
DB7
DB6
VDRIVE
DB0 (LSB)
DB1
DVDD
DB2
DB3
DB5
DB4
DGND
01
12
8-
00
3
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin
Mnemonic
Function
1 to 3,
13 to 18,
22 to 24
DB11 to DB0
Data Bit 11 to Data Bit 0. Parallel digital outputs that provide the conversion result for the part. These are
three-state outputs that are controlled by CS and RD. The output high voltage level for these outputs is
determined by the VDRIVE input.
4
AVDD
Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on the AD7492.
The AVDD and DVDD voltages should ideally be at the same potential and must not be more than 0.3 V apart,
even on a transient basis. This supply should be decoupled to AGND.
5
REF OUT
Reference Out. The output voltage from this pin is 2.5 V ± 1%.
6
VIN
Analog Input. Single-ended analog input channel. The input range is 0 V to REFIN. The analog input presents
a high dc input impedance.
7
AGND
Analog Ground. Ground reference point for all analog circuitry on the AD7492. All analog input signals
should be referred to this AGND voltage. The AGND and DGND voltages should ideally be at the same
potential and must not be more than 0.3 V apart, even on a transient basis.
8
CS
Chip Select. Active low logic input used in conjunction with RD to access the conversion result. The
conversion result is placed on the data bus following the falling edge of both CS and RD. CS and RD are both
connected to the same AND gate on the input so the signals are interchangeable. CS can be hardwired
permanently low.
9
RD
Read Input. Logic input used in conjunction with CS to access the conversion result. The conversion result is
placed on the data bus following the falling edge of both CS and RD. CS and RD are both connected to the
same AND gate on the input so the signals are interchangeable. CS and RD can be hardwired permanently
low, in which case the data bus is always active and the result of the new conversion is clocked out slightly
before to the BUSY line going low.
10
CONVST
Conversion Start Input. Logic input used to initiate conversion. The input track/hold amplifier goes from track
mode to hold mode on the falling edge of CONVST and the conversion process is initiated at this point. The
conversion input can be as narrow as 10 ns. If the CONVST input is kept low for the duration of conversion
and is still low at the end of conversion, the part automatically enters a sleep mode. The type of sleep mode is
determined by the PS/FS pin. If the part enters a sleep mode, the next rising edge of CONVST wakes up the
part. Wake-up time depends on the type of sleep mode.
11
PS/FS
Partial Sleep/Full Sleep Mode. This pin determines the type of sleep mode the part enters if the CONVST pin is
kept low for the duration of the conversion and is still low at the end of conversion. In partial sleep mode the
internal reference circuit and oscillator circuit are not powered down and draws 250 μA maximum. In full
sleep mode all of the analog circuitry are powered down and the current drawn is negligible. This pin is
hardwired either high (DVDD) or low (GND).
12
BUSY
BUSY Output. Logic output indicating the status of the conversion process. The BUSY signal goes high after
the falling edge of CONVST and stays high for the duration of the conversion. Once the conversion is
complete and the conversion result is in the output register, the BUSY line returns low. The track/hold returns
to track mode just prior to the falling edge of BUSY and the acquisition time for the part begins when BUSY
goes low. If the CONVST input is still low when BUSY goes low, the part automatically enters its sleep mode
on the falling edge of BUSY.
19
DGND
Digital Ground. This is the ground reference point for all digital circuitry on the AD7492. The DGND and AGND
voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient
basis.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD7492BR-REEL7 | 功能描述:IC ADC 12BIT W/REF W/CLK 24-SOIC RoHS:否 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:12 采样率（每秒）:300k 数据接口:并联 转换器数目:1 功率耗散（最大）:75mW 电压电源:单电源 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC 包装:带卷 (TR) 输入数目和类型:1 个单端，单极；1 个单端，双极 |
| AD7492BRU | 功能描述:IC ADC 12BIT W/REF W/CLK 24TSSOP RoHS:否 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:12 采样率（每秒）:3M 数据接口:- 转换器数目:- 功率耗散（最大）:- 电压电源:- 工作温度:- 安装类型:表面贴装 封装/外壳:SOT-23-6 供应商设备封装:SOT-23-6 包装:带卷 (TR) 输入数目和类型:- |
| AD7492BRU-5 | 制造商:Analog Devices 功能描述:ADC Single SAR 1.25Msps 12-bit Parallel 24-Pin TSSOP 制造商:Rochester Electronics LLC 功能描述:1.5MSPS 12-BIT ADC, INTERNAL REF + CLOCK - Bulk |
| AD7492BRU-5-REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 1.25Msps 12-bit Parallel 24-Pin TSSOP T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 1.25MSPS 12-BIT PARALLEL 24TSSOP - Tape and Reel |
| AD7492BRU-5-REEL7 | 制造商:Analog Devices 功能描述:ADC Single SAR 1.25Msps 12-bit Parallel 24-Pin TSSOP T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 1.25MSPS 12-BIT PARALLEL 24TSSOP - Tape and Reel |
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