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参数资料
| 型号： | AD7520SD883B |
| 厂商： | Intersil Corporation |
| 英文描述： | 10-Bit, 12-Bit, Multiplying D/A Converters |
| 中文描述： | 10位，12位，乘法D / A转换 |
| 文件页数： | 10/14页 |
| 文件大小： | 264K |
| 代理商： | AD7520SD883B |
Definition of Terms
Resolution:
Resolution is defined as the reciprocal of the
number of discrete steps in the D/A output. It is directly
related to the number of switches or bits within the D/A. For
example, the DAC1020 has 2
10
or 1024 steps while the
DAC1220 has 2
12
or 4096 steps. Therefore, the DAC1020
has 10-bit resolution, while the DAC1220 has 12-bit resolu-
tion.
Linearity Error:
Linearity error is the maximum deviation
from a straight line passing through the endpoints of the
D/A transfer characteristic. It is measured after calibrating
for zero (see V
OS
adjust in typical applications) and full-
scale. Linearity error is a design parameter intrinsic to the
device and cannot be externally adjusted.
Power Supply Sensitivity:
Power supply sensitivity is a
measure of the effect of power supply changes on the D/A
full-scale output.
Settling Time:
Full-scale settling time requires a zero to full-
scale or full-scale to zero output change. Settling time is the
time required from a code transition until the D/A output
reaches within
g
(/2
LSB of final output value.
Full-Scale Error:
Full-scale error is a measure of the output
error between an ideal D/A and the actual device output.
Ideally, for the DAC1020 full-scale is V
REF
b
1 LSB. For
V
REF
e
10V
and
unipolar
LE
10.0000VD9.8 mV
e
9.9902V. Full-scale error is ad-
justable to zero as shown in Figure 5.
operation,
V
FULL-SCA-
TL/H/5689–10
a
b1
b2
(a) End point test after zero and full-scale adjust.
The DAC has 1 LSB linearity error.
(b) By shifting the full-scale calibration on of the DAC of
Figure (b1) we could pass the ‘‘best straight line’’ (b2)
test and meet the
g
(/2
linearity error specification.
Note. (a), (b1) and (b2) above illustrate the difference between ‘‘end point’’ National’s linearity test (a) and ‘‘best straight line’’ test. Note that both devices in (a) and
(b2) meet the
g
(/2
LSB linearity error specification but the end point test is a more ‘‘real life’’ way of characterizing the DAC.
Connection Diagrams
DAC102X
Dual-In-Line Package
TL/H/5689–13
DAC1020
PLCC Package
TL/H/5689–12
DAC122X
Dual-In-Line Package
TL/H/5689–11
http://www.national.com
10
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