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参数资料
| 型号： | AD7568BSZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/14页 |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT OCTAL LC2MOS 44MQFP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 标准包装： | 800 |
| 设置时间： | 500ns |
| 位数： | 12 |
| 数据接口： | 串行 |
| 转换器数目： | 8 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 17.5mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-QFP |
| 供应商设备封装： | 44-MQFP（10x10） |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 16 电流，单极；16 电流，双极 |
| 采样率（每秒）： | 2M |
AD7568
–9–
Current Mode Circuit
In the current mode circuit of Figure 17, IOUT2, and hence
IOUT1, is biased positive by an amount VBIAS. For the circuit to
operate correctly, the DAC ladder termination resistor must be
connected internally to IOUT2. This is the case with the AD7568.
The output voltage is given by:
VOUT = D
RFB
RDAC
V BIAS V IN
()
{}+V
BIAS
As D varies from 0 to 4095/4096, the output voltage varies from
VOUT = VBIAS to VOUT = 2 VBIAS – VIN. VBIAS should be a low
impedance source capable of sinking and sourcing all possible
variations in current at the IOUT2 terminal without any
problems.
Voltage Mode Circuit
Figure 18 shows DAC A of the AD7568 operating in the
voltage-switching mode. The reference voltage, VIN is applied to
the IOUT1 pin, IOUT2 is connected to AGND and the output volt-
age is available at the VREF terminal. In this configuration, a
positive reference voltage results in a positive output voltage
making single supply operation possible. The output from the
DAC is a voltage at a constant impedance (the DAC ladder re-
sistance). Thus, an op amp is necessary to buffer the output
voltage. The reference voltage input no longer sees a constant
input impedance, but one which varies with code. So, the volt-
age input should be driven from a low impedance source.
It is important to note that VIN is limited to low voltages be-
cause the switches in the DAC no longer have the same source-
drain voltage. As a result, their on-resistance differs and this
degrades the integral linearity of the DAC. Also, VIN must not
go negative by more than 0.3 volts or an internal diode will turn
on, causing possible damage to the device. This means that the
full-range multiplying capability of the DAC is lost.
DAC A
A1
I
A
OUT1
I
A
OUT2
AD7568
V
OUT
R
A
FB
V
A
REF
V
IN
NOTES
1) ONLY ONE DAC IS SHOWN FOR CLARITY.
2) DIGITAL INPUT CONNECTIONS ARE OMITTED.
3) C1 PHASE COMPENSATION (5–15pF) MAY BE
REQUIRED WHEN USING HIGH SPEED AMPLIFIER, A1.
R1
R2
Figure 18. Single Supply Voltage Switching
Mode Operation
APPLICATIONS
Programmable State Variable Filter
The AD7568 with its multiplying capability and fast settling
time is ideal for many types of signal conditioning applications.
The circuit of Figure 19 shows its use in a state variable filter
design. This type of filter has three outputs: low pass, high pass
and bandpass. The particular version shown in Figure 19 uses
one half of an AD7568 to control the critical parameters f0, Q
and A0. Instead of several fixed resistors, the circuit uses the
DAC equivalent resistances as circuit elements. Thus, R1 in
Figure 19 is controlled by the 12-bit digital word loaded to
DAC A of the AD7568. This is also the case with R2, R3 and
R4. The fixed resistor R5 is the feedback resistor, RFBB.
DAC Equivalent Resistance, REQ = (RLADDER
4096)/N
where:
RLADDER is the DAC ladder resistance.
N is the DAC Digital Code in Decimal (0 < N < 4096).
DAC A
(R1)
DAC B
(R2)
1/2 x AD7568
A1
R8 30k
HIGH
PASS
OUTPUT
DAC C
(R3)
I
A
OUT1
I
C
OUT1
R
B
FB
V
B
REF
V
IN
I
B
OUT1
V
C
REF
DAC D
(R4)
C3 10pF
C1 1000pF
R7 30k
C1 1000pF
LOW
PASS
OUTPUT
BAND
PASS
OUTPUT
V
A
REF
I
C
OUT2
I
B
OUT2
I
A
OUT2
I
D
OUT2
V
D
REF
I
D
OUT1
A2
A3
R6
10k
NOTES
1. A1, A2, A3, A4: 1/4 x AD713
2. DIGITAL INPUT CONNECTIONS ARE OMITTED.
3. C3 IS A COMPENSATION CAPACITOR TO ELIMINATE
Q AND GAIN VARIATIONS CAUSED BY AMPLIFIER GAIN
BANDWIDTH LIMITATIONS.
Figure 19. Programmable 2nd Order State Variable Filter
REV. C
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