参数资料
| 型号： | AD7610BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 32/32页 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT 250KSPS 48-LFCSP |
| 标准包装： | 1 |
| 系列： | PulSAR® |
| 位数： | 16 |
| 采样率（每秒）： | 250k |
| 数据接口： | 串行，并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 110mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-VQ（7x7） |
| 包装： | 托盘 |
| 输入数目和类型： | 1 个差分，单极；1 个差分，双极 |
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Data Sheet
AD7610
Rev. A | Page 9 of 32
Pin No.
Mnemonic
Type1
Description
14
D5 or
DI/O
In parallel mode, this output is used as Bit 5 of the parallel port data output bus.
INVSYNC
Serial Data Invert Sync Select. In serial master mode (SER/PAR = high, EXT/INT = low). This input is used to
select the active state of the SYNC signal.
When INVSYNC = low, SYNC is active high.
When INVSYNC = high, SYNC is active low.
15
D6 or
DI/O
In parallel mode, this output is used as Bit 6 of the parallel port data output bus.
INVSCLK
In all serial modes, invert SDCLK/SCCLK select. This input is used to invert both SDCLK and SCCLK.
When INVSCLK = low, the rising edge of SDCLK/SCCLK are used.
When INVSCLK = high, the falling edge of SDCLK/SCCLK are used.
16
D7 or
DI/O
In parallel mode, this output is used as Bit 7 of the parallel port data output bus.
RDC or
Serial Data Read During Convert. In serial master mode (SER/PAR = high, EXT/INT = low) RDC is used to select
the read mode. See the
When RDC = low, the current result is read after conversion. Note the maximum throughput is not attainable
in this mode.
When RDC = high, the previous conversion result is read during the current conversion.
SDIN
Serial Data In. In serial slave mode (SER/PAR = high EXT/INT = high) SDIN can be used as a data input to daisy-
chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is
output on SDOUT with a delay of 16 SDCLK periods after the initiation of the read sequence.
18
OVDD
P
Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface 2.5 V, 3
V, or 5 V and decoupled with 10 μF and 100 nF capacitors.
19
DVDD
P
Digital Power. Nominally at 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors. Can be supplied
from AVDD.
20
DGND
P
Digital Power Ground. Ground reference point for digital outputs. Should be connected to system digital
ground ideally at the same potential as AGND and OGND.
21
D8 or
DO
In parallel mode, this output is used as Bit 8 of the parallel port data output bus.
SDOUT
Serial Data output. In all serial modes this pin is used as the serial data output synchronized to SDCLK.
Conversion results are stored in an on-chip register. The AD7610 provides the conversion result, MSB first,
from its internal shift register. The data format is determined by the logic level of OB/2C.
When EXT/INT = low, (master mode) SDOUT is valid on both edges of SDCLK.
When EXT/INT = high (slave mode).
When INVSCLK = low, SDOUT is updated on SDCLK rising edge.
When INVSCLK = high, SDOUT is updated on SDCLK falling edge.
22
D9 or
DI/O
In parallel mode, this output is used as Bit 9 of the parallel port data output bus.
SDCLK
Serial Data Clock. In all serial modes, this pin is used as the serial data clock input or output, dependent on the
logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends on the logic state of
the INVSCLK pin.
23
D10 or
DO
In parallel mode, this output is used as Bit 10 of the parallel port data output bus.
SYNC
Serial Data Frame Synchronization. In serial master mode (SER/PAR = high, EXT/INT= low), this output is used
as a digital output frame synchronization for use with the internal data clock.
When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while the SDOUT
output is valid.
When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while the SDOUT
output is valid.
24
D11 or
DO
In parallel mode, this output is used as Bit 11 of the parallel port data output bus.
RDERROR
Serial Data Read Error. In serial slave mode (SER/PAR = high, EXT/INT = high), this output is used as an
incomplete data read error flag. If a data read is started and not completed when the current conversion is
complete, the current data is lost and RDERROR is pulsed high.
25
D12 or
DI/O
In parallel mode, this output is used as Bit 12 of the parallel port data output bus.
HW/SW
Serial Configuration Hardware/Software Select. In serial mode, this input is used to configure the AD7610 by
hardware or software. See the
Hardware Configuration section and Software Configuration section.
When HW/SW = low, the AD7610 is configured through software using the serial configuration register.
When HW/SW = high, the AD7610 is configured through dedicated hardware input pins.
26
D13 or
DI/O
In parallel mode, this output is used as Bit 13 of the parallel port data output bus.
SCIN
Serial Configuration Data Input. In serial software configuration mode (SER/PAR = high, HW/SW = low) this
input is used to serially write in, MSB first, the configuration data into the serial configuration register. The
data on this input is latched with SCCLK. See the
Software Configuration section.
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