参数资料
| 型号： | AD7652ASTZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 11/28页 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT 500KSPS REF 48LQFP |
| 标准包装： | 1 |
| 系列： | PulSAR® |
| 位数： | 16 |
| 采样率（每秒）： | 500k |
| 数据接口： | 串行，并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 90mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 托盘 |
| 输入数目和类型： | 2 个伪差分，单极 |
| 配用： | EVAL-AD7652CBZ-ND - BOARD EVALUATION FOR AD7652 |
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AD7652
POWER DISSIPATION VERSUS THROUGHPUT
The CNVST trace should be shielded with ground and a low
value serial resistor (i.e., 50 ) termination should be added
close to the output of the component that drives this line.
Operating currents are very low during the acquisition phase,
allowing significant power savings when the conversion rate is
reduced (see
). The AD7652 automatically reduces its
power consumption at the end of each conversion phase. This
makes the part ideal for very low power battery applications.
The digital interface and the reference remain active even
during the acquisition phase. To reduce operating digital supply
currents even further, digital inputs need to be driven close to
the power supply rails (i.e., DVDD or DGND), and OVDD
should not exceed DVDD by more than 0.3 V.
Figure 25. Power Dissipation vs. Sampling Rate
For applications where SNR is critical, the CNVST signal should
have very low jitter. This may be achieved by using a dedicated
oscillator for CNVST generation, or to clock CNVST with a
high frequency, low jitter clock, as shown in
BUSY
MODE
t2
t1
t3
t4
t5
t6
t7
t8
ACQUIRE
CONVERT
ACQUIRE
CONVERT
02964-0-011
CNVST
SAMPLE RATE (SPS)
10
02965-0-037
1000000
100
10000
100000
1000
10000
100
1000
100000
10
POW
E
R
DISSIPATION
(
W)
PDREF = PDBUF = HIGH
CONVERSION CONTROL
Figure 26. Basic Conversion Timing
t9
t8
RESET
DATA
BUSY
02964-0-011
CNVST
shows the detailed timing diagrams of the conversion
process. The AD7652 is controlled by the CNVST signal, which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conversion
is complete. CNVST operates independently of CS and RD.
Figure 27. RESET Timing
Conversions can be automatically initiated with the AD7652. If
CNVST is held LOW when BUSY is LOW, the AD7652 controls
the acquisition phase and automatically initiates a new
conversion. By keeping CNVST LOW, the AD7652 keeps the
conversion process running by itself. It should be noted that the
analog input must be settled when BUSY goes LOW. Also, at
power-up, CNVST should be brought LOW once to initiate the
conversion process. In this mode, the AD7652 can run slightly
faster than the guaranteed 500 kSPS.
t1
t3
t4
t11
BUSY
DATA
BUS
CS = RD = 0
t10
PREVIOUS CONVERSION DATA
NEW DATA
02964-0-012
CNVST
Although CNVST is a digital signal, it should be designed with
special care with fast, clean edges, and levels with minimum
overshoot and undershoot or ringing.
Figure 28. Master Parallel Data Timing for Reading (Continuous Read)
Rev. 0 | Page 19 of 28
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD7652ASTZRL | 功能描述:IC ADC 16BIT UNIPOLAR 48LQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:PulSAR® 标准包装:1,000 系列:- 位数:12 采样率（每秒）:300k 数据接口:并联 转换器数目:1 功率耗散（最大）:75mW 电压电源:单电源 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC 包装:带卷 (TR) 输入数目和类型:1 个单端，单极；1 个单端，双极 |
| AD7653 | 制造商:AD 制造商全称:Analog Devices 功能描述:16-Bit 1 MSPS SAR Unipolar ADC with Ref |
| AD7653ACP | 制造商:Analog Devices 功能描述:16BIT SAR ADC REF 7653 LFSCP-48 |
| AD7653ACPRL | 制造商:Analog Devices 功能描述: |
| AD7653ACPZ | 功能描述:IC ADC 16BIT UNIPOLAR 48LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:PulSAR® 其它有关文件:TSA1204 View All Specifications 标准包装:1 系列:- 位数:12 采样率（每秒）:20M 数据接口:并联 转换器数目:2 功率耗散（最大）:155mW 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-TQFP 供应商设备封装:48-TQFP（7x7） 包装:Digi-Reel® 输入数目和类型:4 个单端，单极；2 个差分，单极 产品目录页面:1156 (CN2011-ZH PDF) 其它名称:497-5435-6 |
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