参数资料
型号: AD7653ACPZ
厂商: Analog Devices Inc
文件页数: 7/28页
文件大小: 0K
描述: IC ADC 16BIT UNIPOLAR 48LFCSP
标准包装: 1
系列: PulSAR®
位数: 16
采样率(每秒): 1M
数据接口: 串行,并联
转换器数目: 1
功率耗散(最大): 145mW
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-VFQFN 裸露焊盘,CSP
供应商设备封装: 48-LFCSP-VQ(7x7)
包装: 托盘
输入数目和类型: 2 个伪差分,单极
配用: EVAL-AD7653CBZ-ND - BOARD EVALUATION FOR AD7653
AD7653
CIRCUIT INFORMATION
SWA
COMP
SWB
IN
REF
REFGND
LSB
MSB
32,768C
INGND
16,384C
4C
2C
C
65,536C
CONTROL
LOGIC
SWITCHES
CONTROL
BUSY
OUTPUT
CODE
02966-0-005
CNVST
Figure 20. ADC Simplified Schematic
The AD7653 is a very fast, low power, single supply, precise
16-bit analog-to-digital converter (ADC). The AD7653 features
different modes to optimize performance according to the
application. In Warp mode, the part can convert 1 million
samples per second.
from the inputs and connected to REFGND. Therefore, the
differential voltage between IN and INGND captured at the end
of the acquisition phase is applied to the comparator inputs,
causing the comparator to become unbalanced. By switching
each element of the capacitor array between REFGND and REF,
the comparator input varies by binary weighted voltage steps
(VREF/2, VREF/4, …VREF/65536). The control logic toggles
these switches, starting with the MSB, to bring the comparator
back into a balanced condition.
The AD7653 provides the user with an on-chip track/hold,
successive approximation ADC that does not exhibit any
pipeline or latency, making it ideal for multiple multiplexed
channel applications.
After this process is completed, the control logic generates the
ADC output code and brings the BUSY output LOW.
The AD7653 can be operated from a single 5 V supply and can
be interfaced to either 5 V or 3 V digital logic. It is housed in
either a 48-lead LQFP or a 48-lead LFCSP that saves space and
allows flexible configurations as either a serial or a parallel
interface. The AD7653 is a pin-to-pin compatible upgrade of the
AD7651/AD7652.
Modes of Operation
The AD7653 features three modes of operations: Warp, Normal,
and Impulse. Each mode is best suited for specific applications.
Warp mode allows the fastest conversion rate up to 1 MSPS.
However in this mode and this mode only, the full specified
accuracy is guaranteed only when the time between conversions
does not exceed 1 ms. If the time between two consecutive
conversions is longer than 1 ms (e.g., after power-up), the first
conversion result should be ignored. This mode makes the
AD7653 ideal for applications where both high accuracy and
fast sample rate are required.
CONVERTER OPERATION
The AD7653 is a successive approximation ADC based on a
charge redistribution DAC. F
shows a simplified
schematic of the ADC. The capacitive DAC consists of an array
of 16 binary weighted capacitors and an additional LSB
capacitor. The comparator’s negative input is connected to a
dummy capacitor of the same value as the capacitive DAC array.
Normal mode is the fastest mode (800 kSPS) without any
limitations on the time between conversions. This mode makes
the AD7653 ideal for asynchronous applications such as data
acquisition systems, where both high accuracy and fast sample
rate are required.
During the acquisition phase, the common terminal of the array
tied to the comparator’s positive input is connected to AGND
via SWA. All independent switches are connected to the analog
input IN. Thus, the capacitor array is used as a sampling
capacitor and acquires the analog signal on IN. Similarly, the
dummy capacitor acquires the analog signal on INGND.
Impulse mode, the lowest power dissipation mode, allows power
saving between conversions. When operating at 1 kSPS, for
example, it typically consumes only 138 W. This feature makes
the AD7653 ideal for battery-powered applications.
When CNVST goes LOW, a conversion phase is initiated. When
the conversion phase begins, SWA and SWB are opened. The
capacitor array and dummy capacitor are then disconnected
Rev. A | Page 15 of 28
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