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参数资料
| 型号： | AD7667ASTZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 17/28页 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT UNIPOLAR 48LQFP |
| 标准包装： | 2,000 |
| 系列： | PulSAR® |
| 位数： | 16 |
| 采样率（每秒）： | 1M |
| 数据接口： | 串行，并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 145mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 2 个伪差分，单极 |
| 配用： | EVAL-AD7667CBZ-ND - BOARD EVALUATION FOR AD7667 |
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AD7667
Rev. 0 | Page 24 of 28
SLAVE SERIAL INTERFACE
External Clock
The AD7667 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/INT pin is
held HIGH. In this mode, several methods can be used to read
the data. The external serial clock is gated by CS. When CS and
RD are both LOW, the data can be read after each conversion or
during the following conversion. The external clock can be
either a continuous or a discontinuous clock. A discontinuous
clock can be either normally HIGH or normally LOW when
inactive. Figure 41 and Figure 42 show the detailed timing
diagrams of these methods. Usually, because the AD7667 has a
longer acquisition phase than conversion phase, the data are
read immediately after conversion.
While the AD7667 is performing a bit decision, it is important
that voltage transients be avoided on digital input/output pins
or degradation of the conversion result could occur. This is
particularly important during the second half of the conversion
phase because the AD7667 provides error correction circuitry
that can correct for an improper bit decision made during the
first half of the conversion phase. For this reason, it is
recommended that when an external clock is being provided, it
is a discontinuous clock that is toggling only when BUSY is
LOW, or, more importantly, that it does not transition during
the latter half of BUSY HIGH.
SCLK
SDOUT
D15
D14
D1
D0
D13
X15
X14
X13
X1
X0
Y15
Y14
BUSY
SDIN
INVSCLK = 0
t35
t36 t37
t31
t32
t16
t33
X15
X14
X
1
2
3
14
151617
18
t34
03033-0-034
EXT/INT = 1
RD
RD = 0
Figure 41. Slave Serial Data Timing for Reading (Read after Convert)
SDOUT
SCLK
D1
D0
X
D15
D14
D13
12
3
14
15
16
t3
t35
t36 t37
t31
t32
t16
BUSY
EXT/INT = 1
INVSCLK = 0
03033-0-035
CNVST
CS
RD = 0
Figure 42. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD7669 | 制造商:AD 制造商全称:Analog Devices 功能描述:LC2MOS Complete, 8-Bit Analog I/0 Systems |
| AD7669AN | 制造商:Analog Devices 功能描述:Data Acquisition System Single ADC Dual DAC 8-Bit 28-Pin PDIP W |
| AD7669AR | 功能描述:IC I/O PORT 8BIT ANLG 28-SOIC RoHS:否 类别:集成电路 (IC) >> 接口 - 专用 系列:LC²MOS 特色产品:NXP - I2C Interface 标准包装:1 系列:- 应用:2 通道 I²C 多路复用器 接口:I²C，SM 总线 电源电压:2.3 V ~ 5.5 V 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:剪切带 (CT) 安装类型:表面贴装 产品目录页面:825 (CN2011-ZH PDF) 其它名称:568-1854-1 |
| AD7669AR-REEL | 制造商:Analog Devices 功能描述: |
| AD7669ARZ | 功能描述:IC I/O PORT 8BIT ANALOG 28SOIC RoHS:是 类别:集成电路 (IC) >> 接口 - 专用 系列:LC²MOS 特色产品:NXP - I2C Interface 标准包装:1 系列:- 应用:2 通道 I²C 多路复用器 接口:I²C，SM 总线 电源电压:2.3 V ~ 5.5 V 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:剪切带 (CT) 安装类型:表面贴装 产品目录页面:825 (CN2011-ZH PDF) 其它名称:568-1854-1 |
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