参数资料
| 型号： | AD7671ACPZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 22/24页 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT CMOS 1MSPS 48LFCSP |
| 标准包装： | 2,500 |
| 系列： | PulSAR® |
| 位数： | 16 |
| 采样率（每秒）： | 1M |
| 数据接口： | 串行，并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 125mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-VQ（7x7） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 4 个单端，单极；4 个单端，双极 |
| 配用： | EVAL-AD7671CBZ-ND - BOARD EVALUATION FOR AD7671 |
–7–
AD7671
PIN FUNCTION DESCRIPTION (continued)
Pin
No.
Mnemonic
Type
Description
21
D[8]
DO
When SER/
PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus.
or SDOUT
When SER/
PAR is HIGH, this output, part of the Serial Port, is used as a serial data output
synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7671 provides
the conversion result, MSB first, from its internal shift register. The data format is determined
by the logic level of OB/
2C. In Serial Mode, when EXT/INT is LOW, SDOUT is valid on both
edges of SCLK.
In Serial Mode, when EXT/
INT is HIGH:
If INVSCLK is LOW, SDOUT is updated on SCLK rising edge and valid on the next falling edge.
If INVSCLK is HIGH, SDOUT is updated on SCLK falling edge and valid on the next rising edge.
22
D[9]
DI/O
When SER/
PAR is LOW, this output is used as Bit 9 of the Parallel Port Data Output Bus.
or SCLK
When SER/
PAR is HIGH, this pin, part of the Serial Port, is used as a serial data clock input or
output, dependent upon the logic state of the EXT/
INT pin. The active edge where the data SDOUT
is updated depends upon the logic state of the INVSCLK pin.
23
D[10]
DO
When SER/
PAR is LOW, this output is used as Bit 10 of the Parallel Port Data Output Bus.
or SYNC
When SER
/PAR is HIGH, this output, part of the Serial Port, is used as a digital output frame
synchronization for use with the internal data clock (EXT/
INT = Logic LOW). When a read sequence
is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while SDOUT
output is valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW
and remains LOW while SDOUT output is valid.
24
D[11]
DO
When SER/
PAR is LOW, this output is used as Bit 11 of the Parallel Port Data Output Bus.
or RDERROR
When SER/
PAR is HIGH and EXT/INT is HIGH, this output, part of the Serial Port, is used as an
incomplete read error flag. In Slave Mode, when a data read is started and not complete when the
following conversion is complete, the current data is lost and RDERROR is pulsed HIGH.
25–28
D[12:15]
DO
Bit 12 to Bit 15 of the Parallel Port Data Output Bus. When SER/
PAR is HIGH, these outputs are in
high impedance.
29
BUSY
DO
Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the conversion
is complete and the data is latched into the on-chip shift register. The falling edge of BUSY could
be used as a data-ready clock signal.
30
DGND
P
Must Be Tied to Digital Ground.
31
RD
DI
Read Data. When
CS and RD are both LOW, the Interface Parallel or Serial Output Bus is enabled.
32
CS
DI
Chip Select. When
CS and RD are both LOW, the Interface Parallel or Serial Output Bus is enabled.
CS is also used to gate the external serial clock.
33
RESET
DI
Reset Input. When set to a logic HIGH, reset the AD7671. Current conversion, if any, is aborted.
If not used, this pin could be tied to DGND.
34
PD
DI
Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are
inhibited after the current one is completed.
35
CNVST
DI
Start Conversion. A falling edge on
CNVST puts the internal sample-and-hold into the hold state
and initiates a conversion. In Impulse Mode (IMPULSE HIGH and WARP LOW), if
CNVST is
held LOW when the acquisition phase
(t
8) is complete, the internal sample-and-hold is put into the
hold state and a conversion is immediately started.
36
AGND
P
Must Be Tied to Analog Ground.
37
REF
AI
Reference Input Voltage.
38
REFGND
AI
Reference Input Analog Ground.
39
INGND
P
Analog Input Ground.
40, 41,
INA, INB,
AI
Analog Inputs. Refer to Table I for input range configuration.
42, 43
INC, IND
NOTES
AI = Analog Input
DI = Digital Input
DI/O = Bidirectional Digital
DO = Digital Output
P = Power
REV. C
Paddle connected to AGND for the LFCSP (CP-48-1). This connection is not required to meet the electrical performances.
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相关代理商/技术参数 |
参数描述 |
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| AD7671AST | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 16-bit Parallel/Serial 48-Pin LQFP 制造商:Analog Devices 功能描述:IC 16-BIT ADC |
| AD7671ASTRL | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 16-bit Parallel/Serial 48-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:16-BIT, 1MSPS CMOS ADC - Tape and Reel |
| AD7671ASTZ | 功能描述:IC ADC 16BIT CMOS 1MSPS 48-LQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:PulSAR® 标准包装:1 系列:microPOWER™ 位数:8 采样率（每秒）:1M 数据接口:串行，SPI? 转换器数目:1 功率耗散（最大）:- 电压电源:模拟和数字 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:24-VFQFN 裸露焊盘 供应商设备封装:24-VQFN 裸露焊盘（4x4） 包装:Digi-Reel® 输入数目和类型:8 个单端，单极 产品目录页面:892 (CN2011-ZH PDF) 其它名称:296-25851-6 |
| AD7671ASTZKL1 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD7671ASTZRL | 功能描述:IC ADC 16BIT CMOS 1MSPS 48LQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:PulSAR® 标准包装:1 系列:- 位数:14 采样率（每秒）:83k 数据接口:串行，并联 转换器数目:1 功率耗散（最大）:95mW 电压电源:双 ± 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:28-DIP（0.600"，15.24mm） 供应商设备封装:28-PDIP 包装:管件 输入数目和类型:1 个单端，双极 |
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