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| 型号： | AD7677ASTZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 18/20页 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT 1MSPS DIFF 48-LQFP |
| 标准包装： | 1 |
| 系列： | PulSAR® |
| 位数： | 16 |
| 采样率（每秒）： | 1M |
| 数据接口： | 串行，并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 130mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 托盘 |
| 输入数目和类型： | 1 个差分，双极 |
| 产品目录页面： | 778 (CN2011-ZH PDF) |
| 配用： | EVAL-AD7677CBZ-ND - BOARD EVALUATION FOR AD7677 |
REV. A
AD7677
–7–
PIN FUNCTION DESCRIPTIONS (continued)
Pin
No.
Mnemonic
Type
Description
19
DVDD
P
Digital Power. Nominally at 5 V.
20
DGND
P
Digital Power Ground
21
DATA[8]
DO
When SER/
PAR is LOW, this output is used as the Bit 8 of the Parallel Port Data Output Bus.
or SDOUT
When SER/
PAR is HIGH, this output, part of the serial port, is used as a serial data output
synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7677
provides the conversion result, MSB first, from its internal shift register. The DATA format is
determined by the logic level of OB/
2C. In serial mode, when EXT/INT is LOW, SDOUT
is valid on both edges of SCLK. In serial mode, when EXT/
INT is HIGH: If INVSCLK is
LOW, SDOUT is updated on SCLK rising edge and valid on the next falling edge. If INVSCLK
is HIGH, SDOUT is updated on SCLK falling edge and valid on the next rising edge.
22
DATA[9]
DI/O
When SER/
PAR is LOW, this output is used as the Bit 9 of the Parallel Port Data Output Bus.
or SCLK
When SER/
PAR is HIGH, this pin, part of the serial port, is used as a serial data clock input
or output, dependent upon the logic state of the EXT/
INT pin. The active edge where the
data SDOUT is updated depends upon the logic state of the INVSCLK pin.
23
DATA[10]
DO
When SER/
PAR is LOW, this output is used as the Bit 10 of the Parallel Port Data Output Bus.
or SYNC
When SER/
PAR is HIGH, this output, part of the serial port, is used as a digital output frame
synchronization for use with the internal data clock (EXT/
INT = Logic LOW). When a read
sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH
while SDOUT output is valid. When a read sequence is initiated and INVSYNC is HIGH,
SYNC is driven LOW and remains LOW while SDOUT output is valid.
24
DATA[11]
DO
When SER/
PAR is LOW, this output is used as the Bit 11 of the Parallel Port Data Output Bus.
or RDERROR
When SER/
PAR is HIGH and EXT/INT is HIGH, this output, part of the serial port, is used
as an incomplete read error flag. In slave mode, when a data read is started and not complete
when the following conversion is complete, the current data is lost and RDERROR is pulsed high.
25–28
DATA[12:15]
DO
Bit 12 to Bit 15 of the Parallel Port Data Output Bus. These pins are always outputs regard-
less of the state of SER/
PAR.
29
BUSY
DO
Busy Output. Transitions HIGH when a conversion is started, and remains HIGH until the
conversion is complete and the data is latched into the on-chip shift register. The falling edge
of BUSY could be used as a data ready clock signal.
30
DGND
P
Must be tied to digital ground.
31
RD
DI
Read Data. When
CS and RD are both LOW, the interface parallel or serial output bus is enabled.
32
CS
DI
Chip Select. When
CS and RD are both LOW, the interface parallel or serial output bus is
enabled.
CS is also used to gate the external serial clock.
33
RESET
DI
Reset Input. When set to a logic HIGH, reset the AD7677. Current conversion if any is aborted.
34
PD
DI
Power-Down Input. When set to a logic HIGH, power consumption is reduced and conver-
sions are inhibited after the current one is completed.
35
CNVST
DI
Start Conversion. A falling edge on
CNVST puts the internal sample/hold into the hold state and
initiates a conversion. In impulse mode (IMPULSE HIGH and WARP LOW), if
CNVST is
held low when the acquisition phase
(t
8) is complete, the internal sample/hold is put into the
hold state and a conversion is immediately started.
36
AGND
P
Must be Tied to Analog Ground.
37
REF
AI
Reference Input Voltage
38
REFGND
AI
Reference Input Analog Ground
39
IN–
AI
Differential Negative Analog Input
43
IN+
AI
Differential Positive Analog Input
NOTES
AI = Analog Input
DI = Digital Input
DI/O = Bidirectional Digital
DO = Digital Output
P = Power
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD7677ASTZ | 制造商:Analog Devices 功能描述:IC 16-BIT ADC |
| AD7677ASTZRL | 功能描述:IC ADC 16BIT 1MSPS DIFF 48-LQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:PulSAR® 标准包装:1 系列:- 位数:14 采样率（每秒）:83k 数据接口:串行，并联 转换器数目:1 功率耗散（最大）:95mW 电压电源:双 ± 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:28-DIP（0.600"，15.24mm） 供应商设备封装:28-PDIP 包装:管件 输入数目和类型:1 个单端，双极 |
| AD7678 | 制造商:AD 制造商全称:Analog Devices 功能描述:18-Bit, 2.5 LSB INL, 570 kSPS SAR ADC |
| AD7678ACP | 制造商:Analog Devices 功能描述:ADC Single SAR 100ksps 18-bit Parallel/Serial 48-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:18-BIT,100KSPSSARADC - Bulk 制造商:Analog Devices 功能描述:18BIT SAR ADC SMD 7678 LFSCP-48 |
| AD7678ACPRL | 制造商:Analog Devices 功能描述:ADC Single SAR 100ksps 18-bit Parallel/Serial 48-Pin LFCSP EP T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 100KSPS 18BIT PARALLEL/SERL 48LFCSP EP - Tape and Reel 制造商:Rochester Electronics LLC 功能描述:18-BIT,100KSPSSARADC - Bulk |
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