参数资料
型号: AD7679ACPZRL
厂商: Analog Devices Inc
文件页数: 14/28页
文件大小: 0K
描述: IC ADC 18BIT SAR W/BUFF 48LFCSP
标准包装: 2,500
系列: PulSAR®
位数: 18
采样率(每秒): 570k
数据接口: 串行,并联
转换器数目: 1
功率耗散(最大): 103mW
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-VFQFN 裸露焊盘,CSP
供应商设备封装: 48-LFCSP-VQ(7x7)
包装: 带卷 (TR)
输入数目和类型: 1 个差分,双极
配用: EVAL-AD7679CBZ-ND - BOARD EVALUATION FOR AD7679
AD7679
Rev. A | Page 21 of 28
In Read during Conversion mode, the serial clock and data
toggle at appropriate instants, minimizing potential
feedthrough between digital activity and critical conversion
decisions.
MASTER SERIAL INTERFACE
Internal Clock
The AD7679 is configured to generate and provide the serial
data clock SCLK when the EXT/INT pin is held low. The
AD7679 also generates a SYNC signal to indicate to the host
when the serial data is valid. The serial clock SCLK and the
SYNC signal can be inverted if desired. Depending on the
RDC/SDIN input, the data can be read after each conversion or
during the following conversion.
and
the detailed timing diagrams of these two modes.
In Read after Conversion mode, it should be noted that unlike
in other modes, the BUSY signal returns low after the 18 data
bits are pulsed out and not at the end of the conversion phase,
which results in a longer BUSY width.
To accommodate slow digital hosts, the serial clock can be
slowed down by using DIVSCLK.
Usually, because the AD7679 is used with a fast throughput, the
mode master read during conversion is the most recommended
serial mode.
t3
BUSY
CS, RD
CNVST
SYNC
SCLK
SDOUT
12
3
16
17
18
D17
D16
D2
D1
D0
X
EXT/INT = 0
RDC/SDIN = 0
INVSCLK = INVSYNC = 0
t14
t20
t15
t16
t22
t23
t29
t28
t18
t19
t21
t30
t25
t24
t26
t27
03085-0-040
Figure 38. Master Serial Data Timing for Reading (Read after Convert)
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