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| 型号： | AD7686BCPZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/28页 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT 500KSPS 10-LFCSP |
| 标准包装： | 5,000 |
| 系列： | PulSAR® |
| 位数： | 16 |
| 采样率（每秒）： | 500k |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 21.5mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-WFDFN 裸露焊盘，CSP |
| 供应商设备封装： | 10-LFCSP-WD（3x3） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个伪差分，单极 |
| 配用： | EVAL-AD7686CBZ-ND - BOARD EVALUATION FOR AD7686 |
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AD7686
Rev. B | Page 22 of 28
CHAIN MODE WITH BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7686s
on a 3-wire serial interface while providing a busy indicator.
This feature is useful for reducing component count and
wiring connections, for example, in isolated multiconverter
applications or for systems with a limited interfacing capacity.
Data readback is analogous to clocking a shift register. A
connection diagram example using three AD7686s is shown in
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the busy indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
completed their conversions, the nearend ADC (ADC C in
Figure 43) SDO is driven high.
This transition on SDO can be used as a busy indicator to
trigger the data readback controlled by the digital host. The
AD7686 then enters the acquisition phase and powers down.
The data bits stored in the internal shift register are then
clocked out, MSB first, by subsequent SCK falling edges. For
each ADC, SDI feeds the input of the internal shift register and
is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 16 × N + 1 clocks are required to
readback the N ADCs.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate and, consequently, more AD7686s in the chain, provided
the digital host has an acceptable hold time. For instance,
with a 3 ns digital host setup time and 3 V interface, up to four
AD7686s running at a conversion rate of 360 kSPS can be daisy
chained to a single 3-wire port.
CLK
CONVERT
DATA IN
IRQ
DIGITAL HOST
02
96
9-
04
4
CNV
SCK
SDO
SDI
AD7686
C
CNV
SCK
SDO
SDI
AD7686
A
CNV
SCK
SDO
SDI
AD7686
B
Figure 43. Chain Mode with Busy Indicator Connection Diagram
SDOA = SDIB
DA15 DA14 DA13
SCK
12
3
35
47
48
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
CNV = SDIA
DA1
415
tSCK
tSCKH
tSCKL
DA0
17
34
16
SDOB = SDIC
DB15 DB14 DB13
DA1
DB1DB0DA15 DA14
49
tSSDISCK
tHSDISCK
tHSDO
tDSDO
SDOC
DC15 DC14 DC13
DA1DA0
DC1DC0DA14
19
31
32
18
33
DB1DB0DA15
DB15 DB14
tDSDOSDI
tSSCKCNV
tHSCKCNV
0
29
69
-04
5
DA0
tDSDOSDI
Figure 44. Chain Mode with Busy Indicator Serial Interface Timing
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相关代理商/技术参数 |
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|---|---|
| AD7686BCPZRL1 | 制造商:AD 制造商全称:Analog Devices 功能描述:16-Bit, 500 kSPS PulSAR ADC in MSOP/QFN |
| AD7686BCPZRL7 | 功能描述:IC ADC 16BIT 500KSPS 10-LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:PulSAR® 标准包装:1,000 系列:- 位数:12 采样率（每秒）:300k 数据接口:并联 转换器数目:1 功率耗散（最大）:75mW 电压电源:单电源 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC 包装:带卷 (TR) 输入数目和类型:1 个单端，单极；1 个单端，双极 |
| AD7686BCPZRL71 | 制造商:AD 制造商全称:Analog Devices 功能描述:16-Bit, 500 kSPS PulSAR ADC in MSOP/QFN |
| AD7686BRM | 制造商:Analog Devices 功能描述:ADC Single SAR 500ksps 16-bit Serial 10-Pin MSOP Tube |
| AD7686BRMRL7 | 制造商:Analog Devices 功能描述:ADC Single SAR 500ksps 16-bit Serial 10-Pin MSOP T/R |
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