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参数资料
| 型号： | AD7686CRMZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/28页 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT 500KSPS 10MSOP |
| 标准包装： | 1 |
| 系列： | PulSAR® |
| 位数： | 16 |
| 采样率（每秒）： | 500k |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 21.5mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 10-MSOP |
| 包装： | 管件 |
| 输入数目和类型： | 1 个伪差分，单极 |
| 配用： | EVAL-AD7686CBZ-ND - BOARD EVALUATION FOR AD7686 |
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AD7686
Rev. B | Page 18 of 28
CS MODE 3-WIRE WITH BUSY INDICATOR
This mode is generally used when a single AD7686 is connected
to an SPI-compatible digital host having an interrupt input. The
connection diagram is shown in Figure 35, and the correspond-
ing timing is provided in Figure 36.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion, irrespective of the state of CNV.
Prior to the minimum conversion time, CNV can be used to
select other SPI devices, such as analog multiplexers. However,
CNV must be returned low before the minimum conversion
time and held low until the maximum conversion time to
guarantee the generation of the busy signal indicator. When the
conversion is complete, SDO goes from high impedance to low.
With a pull-up on the SDO line, this transition can be used as
an interrupt signal to initiate the data reading controlled by the
digital host. The AD7686 then enters the acquisition phase and
powers down. The data bits are then clocked out, MSB first, by
subsequent SCK falling edges. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the optional
17th SCK falling edge or when CNV goes high, whichever
occurs first, SDO returns to high impedance.
If multiple AD7686s are selected at the same time, the SDO
output pin handles this connection without damage or induced
latch-up. Meanwhile, it is recommended to keep this connection as
short as possible to limit extra power dissipation.
DATA IN
IRQ
CLK
CONVERT
VIO
DIGITAL HOST
02
969
-03
6
47k
CNV
SCK
SDO
SDI
VIO
AD7686
Figure 35. CS Mode 3-Wire with Busy Indicator
Connection Diagram (SDI High)
SDO
D15
D14
D1
D0
tDIS
SCK
1
2
3
15
16
17
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
CNV
CONVERSION
ACQUISITION
tCONV
tCYC
tCNVH
tACQ
ACQUISITION
SDI = 1
0
29
69
-03
7
Figure 36. CS Mode 3-Wire with Busy Indicator Serial Interface Timing (SDI High)
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相关代理商/技术参数 |
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| AD7686CRMZ1 | 制造商:AD 制造商全称:Analog Devices 功能描述:16-Bit, 500 kSPS PulSAR ADC in MSOP/QFN |
| AD7686CRMZRL7 | 功能描述:IC ADC 16BIT 500KSPS 10MSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:PulSAR® 标准包装:1,000 系列:- 位数:12 采样率（每秒）:300k 数据接口:并联 转换器数目:1 功率耗散（最大）:75mW 电压电源:单电源 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC 包装:带卷 (TR) 输入数目和类型:1 个单端，单极；1 个单端，双极 |
| AD7686CRMZRL71 | 制造商:AD 制造商全称:Analog Devices 功能描述:16-Bit, 500 kSPS PulSAR ADC in MSOP/QFN |
| AD7686XRM-U4 | 制造商:Analog Devices 功能描述:500 KSPS 16-BIT PULSAR? A/D CONVERTER IN ?SOIC/CSP - Rail/Tube |
| AD7686XRM-U5 | 制造商:Analog Devices 功能描述:500 KSPS 16-BIT PULSAR? A/D CONVERTER IN ?SOIC/CSP - Bulk |
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