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参数资料
| 型号： | AD7686CRMZRL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/28页 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT 500KSPS 10MSOP |
| 标准包装： | 1,000 |
| 系列： | PulSAR® |
| 位数： | 16 |
| 采样率（每秒）： | 500k |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 21.5mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 10-MSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个伪差分，单极 |
| 配用： | EVAL-AD7686CBZ-ND - BOARD EVALUATION FOR AD7686 |
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AD7686
Rev. B | Page 21 of 28
CHAIN MODE, NO BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7686s on a
3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7686s is shown in
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the busy indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
readback.
When the conversion is complete, the MSB is output onto SDO,
and the AD7686 enters the acquisition phase and powers down.
The remaining data bits stored in the internal shift register are
then clocked by subsequent SCK falling edges. For each ADC,
SDI feeds the input of the internal shift register and is clocked
by the SCK falling edge. Each ADC in the chain outputs its data
MSB first, and 16 × N clocks are required to read back the N
ADCs. The data is valid on both SCK edges. Although the rising
edge can be used to capture the data, a digital host using the
SCK falling edge allows a faster reading rate and, consequently,
more AD7686s in the chain, provided the digital host has an
acceptable hold time. The maximum conversion rate can be
reduced due to the total readback time. For instance, with a 3 ns
digital host setup time and 3 V interface, up to four AD7686s
running at a conversion rate of 360 kSPS can be daisy-chained
on a 3-wire port.
CLK
CONVERT
DATA IN
DIGITAL HOST
029
69
-04
2
CNV
SCK
SDO
SDI
AD7686
B
CNV
SCK
SDO
SDI
AD7686
A
Figure 41. Chain Mode, No Busy Indicator Connection Diagram
SDOA = SDIB
DA15
DA14
DA13
SCK
1
2
3
303132
tSSDISCK
tHSDISCK
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
CNV
DA1
14
15
tSCK
tSCKL
tSCKH
DA0
17
18
16
SDIA = 0
SDOB
DB15
DB14
DB13
DA1
DB1DB0DA15
DA14
tHSDO
tDSDO
tSSCKCNV
tHSCKCNV
DA0
02
96
9-
0
43
Figure 42. Chain Mode, No Busy Indicator Serial Interface Timing
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相关代理商/技术参数 |
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|---|---|
| AD7686CRMZRL71 | 制造商:AD 制造商全称:Analog Devices 功能描述:16-Bit, 500 kSPS PulSAR ADC in MSOP/QFN |
| AD7686XRM-U4 | 制造商:Analog Devices 功能描述:500 KSPS 16-BIT PULSAR? A/D CONVERTER IN ?SOIC/CSP - Rail/Tube |
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| AD7687 | 制造商:AD 制造商全称:Analog Devices 功能描述:3mW, 100kSPS, 14-Bit ADC in 6-Lead SOT-23 |
| AD76871 | 制造商:AD 制造商全称:Analog Devices 功能描述:18-Bit, 2 MSPS PulSAR 15 mW ADC in LFCSP (QFN) |
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