参数资料
型号: AD7687BCPZRL
厂商: Analog Devices Inc
文件页数: 10/28页
文件大小: 0K
描述: IC ADC 16BIT SAR 250KSPS 10LFCSP
标准包装: 5,000
系列: PulSAR®
位数: 16
采样率(每秒): 250k
数据接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
功率耗散(最大): 12.5mW
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 10-WFDFN 裸露焊盘,CSP
供应商设备封装: 10-LFCSP-WD(3x3)
包装: 带卷 (TR)
输入数目和类型: 1 个差分,双极
配用: EVAL-AD7687CBZ-ND - BOARD EVALUATION FOR AD7687
AD7687
Data Sheet
Rev. B | Page 18 of 28
CS MODE 3-WIRE, NO BUSY INDICATOR
This mode is usually used when a single AD7687 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 35 and the corresponding timing is given in
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. Once a conversion is initiated, it continues to
completion irrespective of the state of CNV. For instance, it
could be useful to bring CNV low to select other SPI devices,
such as analog multiplexers, but CNV must be returned high
before the minimum conversion time and held high until the
maximum conversion time to avoid the generation of the BUSY
signal indicator. When the conversion is complete, the AD7687
enters the acquisition phase and powers down. When CNV
goes low, the MSB is output onto SDO. The remaining data bits
are then clocked by subsequent SCK falling edges. The data is
valid on both SCK edges. Although the rising edge can be used
to capture the data, a digital host using the SCK falling edge
allows a faster reading rate provided it has an acceptable hold
time. After the 16th SCK falling edge or when CNV goes high,
whichever is earlier, SDO returns to high impedance.
CNV
SCK
SDO
SDI
DATA IN
CLK
CONVERT
VIO
DIGITAL HOST
AD7687
02972-
034
Figure 35. CS Mode 3-Wire, No BUSY Indicator
Connection Diagram (SDI High)
SDO
D15
D14
D13
D1
D0
tDIS
SCK
1
2
3
14
15
16
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
CNV
CONVERSION
ACQUISITION
tCONV
tCYC
ACQUISITION
SDI = 1
tCNVH
tACQ
tEN
02972-
035
Figure 36. CS Mode 3-Wire, No BUSY Indicator Serial Interface Timing (SDI High)
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