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| 型号： | AD7689BCPZRL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 2/32页 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT 250KSPS 8CH 20LFCSP |
| 产品培训模块： | Power Line Monitoring Motor Control |
| 产品变化通告： | Startup Circuitry Design Improvement Change 15/April/2009 |
| 标准包装： | 1 |
| 系列： | PulSAR® |
| 位数： | 16 |
| 采样率（每秒）： | 250k |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 21mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 20-LFCSP-VQ |
| 包装： | 标准包装 |
| 输入数目和类型： | 8 个单端，单极；4 个差分，双极；4 个伪差分，双极 |
| 其它名称： | AD7689BCPZRL7DKR |
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AD7682/AD7689
Data Sheet
Rev. D | Page 10 of 32
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1
VDD
2
REF
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD IS NOT CONNECTED
INTERNALLY. FOR INCREASED
RELIABILITY OF THE SOLDER JOINTS, IT
IS RECOMMENDED THAT THE PAD BE
SOLDERED TO THE SYSTEM
GROUND PLANE.
3
REFIN
4
GND
5
GND
13 SCK
14 SDO
15 VIO
12 DIN
11 CNV
6
N
C
7
IN
2
8
N
C
01
C
O
M
9
IN
3
81
IN
1
91
N
C
02
V
D
7
1
N
C
61
IN
0
TOP VIEW
(Not to Scale)
AD7682
07
35
3-
0
04
Figure 4. AD7682 Pin Configuration
PIN 1
INDICATOR
1
VDD
2
REF
3
REFIN
4
GND
5
GND
13 SCK
14 SDO
15 VIO
12 DIN
11 CNV
6
IN
4
7
IN
5
8
IN
6
01
C
O
M
9
IN
7
81
IN
2
91
IN
3
02
V
D
7
1
IN
1
61
IN
0
TOP VIEW
(Not to Scale)
AD7689
07
35
3-
00
5
NOTES
1. THE EXPOSED PAD IS NOT CONNECTED
INTERNALLY. FOR INCREASED
RELIABILITY OF THE SOLDER JOINTS, IT
IS RECOMMENDED THAT THE PAD BE
SOLDERED TO THE SYSTEM
GROUND PLANE.
Figure 5. AD7689 Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
Mnemonic
Type1
1, 20
VDD
P
Power Supply. Nominally 2.5 V to 5.5 V when using an external reference and decoupled
with 10 μF and 100 nF capacitors.
When using the internal reference for a2.5 V output, the minimum should be 3.0 V.
When using the internal reference for 4.096 V output, the minimum should be 4.6 V.
2
REF
AI/O
Reference Input/Output. See the Voltage Reference Output/Input section.
When the internal reference is enabled, this pin produces a selectable system reference of
2.5 V or 4.096 V.
When the internal reference is disabled and the buffer is enabled, REF produces a
buffered version of the voltage present on the REFIN pin (VDD 0.5 V maximum), which
is useful when using low cost, low power references.
For improved drift performance, connect a precision reference to REF (0.5 V to VDD).
For any reference method, this pin needs decoupling with an external 10 μF capacitor
connected as close to REF as possible. See the Reference Decoupling section.
3
REFIN
AI/O
Internal Reference Output/Reference Buffer Input. See the Voltage Reference
Output/Input section.
When using the internal reference, the internal unbuffered reference voltage is present
and needs decoupling with a 0.1 μF capacitor.
When using the internal reference buffer, apply a source between 0.5 V and (VDD 0.5 V)
that is buffered to the REF pin, as described in the REF pin description.
4, 5
GND
P
Power Supply Ground.
6
NC
IN4
AI
AD7682: no connection.
AD7689: Analog Input Channel 4.
7
IN2
IN5
AI
AD7682: Analog Input Channel 2.
AD7689: Analog Input Channel 5.
8
NC
IN6
AI
AD7682: no connection.
AD7689: Analog Input Channel 6.
9
IN3
IN7
AI
AD7682: Analog Input Channel 3.
AD7689: Analog Input Channel 7.
10
COM
AI
Common Channel Input. All input channels, IN[7:0], can be referenced to a common-
mode point of 0 V or VREF/2 V.
11
CNV
DI
Conversion Input. On the rising edge, CNV initiates the conversion. During conversion, if
CNV is held low, the busy indictor is enabled.
12
DIN
DI
Data Input. This input is used for writing to the 14-bit configuration register. The
configuration register can be written to during and after conversion.
13
SCK
DI
Serial Data Clock Input. This input is used to clock out the data on SDO and clock in data
on DIN in an MSB first fashion.
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