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| 型号： | AD7708BRZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/44页 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT R-R 8/10CH 28SOIC |
| 标准包装： | 1,000 |
| 位数： | 16 |
| 采样率（每秒）： | 1.37k |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 3.84mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC W |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 4 个差分，单极；4 个差分，双极；8 个伪差分，单极；8 个伪差分，双极 |
| 配用： | EVAL-AD7708EBZ-ND - BOARD EVAL FOR AD7708 |
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REV. 0
–20–
AD7708/AD7718
FREQUENCY – Hz
0
–80
–160
0
100
10
A
TTENUA
TION
–
dB
20
30
40
50
60
70
80
90
–20
–40
–120
–140
–60
–100
SF = 68
OUTPUT DATA RATE = 60.2Hz
SETTLING TIME = 49.8ms
INPUT BANDWIDTH = 15.5Hz
50Hz REJECTION = –43dB, 50Hz 1Hz REJECTION = –40dB
60Hz REJECTION = –147dB, 60Hz 1Hz REJECTION = –101dB
–200
–180
Figure 11. Frequency Response Operating with the
SF Word of 68
FREQUENCY – Hz
0
–80
–160
0
100
10
A
TTENUA
TION
–
dB
20
30
40
50
60
70
80
90
–20
–40
–120
–140
–60
–100
SF = 75
OUTPUT DATA RATE = 54.6Hz
SETTLING TIME = 55ms
INPUT BANDWIDTH = 14.3Hz
50Hz REJECTION = –62.5dB, 50Hz 1Hz REJECTION = –57dB
60Hz REJECTION = –63dB, 60Hz 1Hz REJECTION = –60dB
–200
–180
Figure 12. Optimizing Filter Response for Throughput
while Maximizing the Simultaneous 50 Hz and 60 Hz
Rejection
FREQUENCY – Hz
0
–80
–160
0
100
10
A
TTENUA
TION
–
dB
20
30
40
50
60
70
80
90
–20
–40
–120
–140
–60
–100
SF = 151
OUTPUT DATA RATE = 27.12Hz
SETTLING TIME = 110ms
INPUT BANDWIDTH = 27.12Hz
50Hz REJECTION = –65.4dB, 50Hz 1Hz REJECTION = –60dB
60Hz REJECTION = –63dB, 60Hz 1Hz REJECTION = –60dB
–200
–180
Figure 13. Optimizing Filter Response for Maximum
Simultaneous 50 Hz and 60 Hz Rejection
FREQUENCY – Hz
0
–80
–160
0
100
10
A
TTENUA
TION
–
dB
20
30
40
50
60
70
80
90
–20
–40
–120
–140
–60
–100
SF = 255
OUTPUT DATA RATE = 16.06Hz
SETTLING TIME = 186ms
INPUT BANDWIDTH = 4.21Hz
50Hz REJECTION = –87dB, 50Hz 1Hz REJECTION = –77dB
60Hz REJECTION = –72dB, 60Hz 1Hz REJECTION = –68dB
–200
–180
Figure 14. Frequency with Maximum SF Word = 255
ADC NOISE PERFORMANCE CHOP DISABLED
(
CHOP = 1)
Tables VII to X show the output rms noise and output peak-to-
peak resolution in bits (rounded to the nearest 0.5 LSB) for
some typical output update rates. The numbers are typical and
generated at a differential input voltage of 0 V. The output update
rate is selected via the SF7–SF0 bits in the Filter Register. It is
important to note that the peak-to-peak resolution figures represent
the resolution for which there will be no code flicker within a
six-sigma limit. The output noise comes from two sources. The
first is the electrical noise in the semiconductor devices (device
noise) used in the implementation of the modulator. Secondly,
when the analog input is converted into the digital domain,
quantization noise is added. The device noise is at a low level
and is independent of frequency. The quantization noise starts
at an even lower level but rises rapidly with increasing frequency
to become the dominant noise source. The numbers in the
tables are given for the bipolar input ranges. For the unipolar
ranges the rms noise numbers will be the same as the bipolar
range, but the peak-to-peak resolution is now based on half the
signal range which effectively means losing 1 bit of resolution.
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