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参数资料
| 型号： | AD7731BRUZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 21/44页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT SIGMA-DELTA 24TSSOP |
| 标准包装： | 1,000 |
| 位数： | 24 |
| 采样率（每秒）： | 6.4k |
| 数据接口： | DSP，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 125mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 3 个差分，单极；3 个差分，双极；5 个伪差分，单极；5 个伪差分，双极 |
| 配用： | EVAL-AD7731EBZ-ND - BOARD EVALUATION FOR AD7731 |
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AD7731
–28–
REV. 0
FASTStep Mode (SKIP = 0, FAST = 1)
The second mode of operation of the second stage filter is in
FASTStep mode which enables it to respond rapidly to step
inputs even when the second stage filter is in the loop. The
FASTStep mode is not relevant with SKIP mode enabled.
The FASTStep mode is enabled by placing a 1 in the FAST
bit of the Filter Register. If the FAST bit is 0, the part continues
to process step inputs with the normal FIR filter as the second
stage filter. With FASTStep mode enabled, the second stage
filter will continue to process steady state inputs with the filter
in its normal FIR mode of operation. However, the part is con-
tinuously monitoring the output of the first stage filter and com-
paring it with the second-previous output. If the difference
between these two outputs is greater than a predetermined
threshold (1% of full scale), the second stage filter switches to a
simple moving average computation. This also happens when a
change in channels takes place regardless of how close the volt-
ages on the two channels are. When the change is detected, the
STDY bit of the Status Register goes to 1.
The initial number of averages in the moving average computa-
tion is either 2 (chop enabled) or 1 (chop disabled). The num-
ber of averages will be held at this value as long as the threshold
is exceeded. Once the threshold is no longer exceeded (the step
on the analog input has settled), the number of outputs used to
compute the moving average output is increased. The first and
second outputs from the first stage filter where the threshold is
no longer exceeded is computed as an average by 2, then 4
outputs with an average of 4, 8 outputs with an average of 8 and
6 outputs with an average of 16. At this time, the second stage
filter reverts back to its normal FIR mode of operation. When
the second stage filter reverts back to the normal FIR, the
STDY
bit of the Status Register goes to 0.
Figure 13 gives an indication of the different responses to a step
input with FASTStep mode enabled and disabled. The verti-
cal axis indicates the settling of the output to the input step
change while the horizontal axis shows how many outputs it
takes for that settling to occur. The positive input step change
occurs at a time coincident with the fifth output.
NUMBER OF OUTPUTS
20000000
15000000
0
025
5
CODE
10
15
20
10000000
5000000
Figure 13. Step Response for FASTStep and Normal
Operation
In FASTStep mode, the part has settled to the new value
much faster. For example, with CHP = 1, the FASTStep
mode settles to its value in two outputs while the normal mode
settling takes 23 outputs. Between the second and 23rd output,
the FASTStep mode produces a settled result but with addi-
tional noise compared to the specified noise level for its operat-
ing conditions. This noise level starts at approximately 3 times
the final noise converging to FIR mode performance. The com-
plete settling time to where the part is back within the specified
noise number, is the same for FASTStep mode and for normal
mode. When switching channels, the profile of Figure 13 will
not be seen. Since the part is synchronized when a channel
change takes place, it will not produce an output until the filter
(either FASTStep or FIR) is settled. Table XVIII gives an
indication of the faster settling time benefits of FASTStep
mode.
As can be seen from Table XVIII, the FASTStep mode gives
a much earlier indication of where the output channel is going
and what its new value is. This feature is very useful in scanning
multiple channels where the user does not have to wait for the
FIR settling time to see if a channel has changed value. In this
case, the part can be set up with CHP = 1, SKIP = 0 and FAST
= 1. This takes advantage of the low drift, better noise immunity
benefits of the CHOP mode. When a change in channels takes
place, the part enters FASTStep mode and provides an output
result in 2
× 1/Output Rate.
Note, if the FAST bit is set and the part operated in single con-
version mode, the AD7731 will continue to output results until
the
STDY bit goes to 0.
Table XVIII. Time to First and Subsequent Outputs Follow-
ing Channel Change
Time
Time to
SKIP
CHP
FAST
to First O/P
1
Subsequent O/Ps
0
24
× SF/f
MOD
SF/fMOD
0
1
0
66
× SF/f
MOD
3
× SF/f
MOD
10
X
2
3
× SF/f
MOD
SF/fMOD
11
X
3
× SF/f
MOD
3
× SF/f
MOD
00
1
3
× SF/f
MOD
SF/fMOD
01
1
6
× SF/f
MOD
3
× SF/f
MOD
1This O/P is fully settled.
2X = Don’t Care.
REV. A
相关PDF资料 |
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| VI-2N0-CU-F3 | CONVERTER MOD DC/DC 5V 200W |
| AD7731BRUZ-REEL | IC ADC 24BIT SIGMA-DELTA 24TSSOP |
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相关代理商/技术参数 |
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| AD7731BRZ | 功能描述:IC ADC 24BIT SIGMA-DELTA 24-SOIC RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1 系列:microPOWER™ 位数:8 采样率（每秒）:1M 数据接口:串行，SPI? 转换器数目:1 功率耗散（最大）:- 电压电源:模拟和数字 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:24-VFQFN 裸露焊盘 供应商设备封装:24-VQFN 裸露焊盘（4x4） 包装:Digi-Reel® 输入数目和类型:8 个单端，单极 产品目录页面:892 (CN2011-ZH PDF) 其它名称:296-25851-6 |
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| AD7731BRZ-REEL | 功能描述:IC ADC 24BIT SIGMA-DELTA 24-SOIC RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:12 采样率（每秒）:300k 数据接口:并联 转换器数目:1 功率耗散（最大）:75mW 电压电源:单电源 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC 包装:带卷 (TR) 输入数目和类型:1 个单端，单极；1 个单端，双极 |
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| AD7731EB | 制造商:AD 制造商全称:Analog Devices 功能描述:Low Noise High Throughput 24-Bit Sigma-Delta ADC(411.99 k) |
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