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| 型号： | AD7731BRUZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 7/44页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT SIGMA-DELTA 24TSSOP |
| 标准包装： | 2,500 |
| 位数： | 24 |
| 采样率（每秒）： | 6.4k |
| 数据接口： | DSP，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 125mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 3 个差分，单极；3 个差分，双极；5 个伪差分，单极；5 个伪差分，双极 |
| 配用： | EVAL-AD7731EBZ-ND - BOARD EVALUATION FOR AD7731 |
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AD7731
–15–
REV. 0
Data Register (RS2-RS0 = 0, 0, 1); Power On/Reset Status: 000000 Hex
The Data Register on the part is a read-only register that contains the most up-to-date conversion result from the AD7731. Figure 5
shows a flowchart for reading from the registers on the AD7731. The register can be programmed to be either 16 or 24 bits wide,
determined by the status of the WL bit of the Mode Register. The
RDY output and RDY bit of the Status Register are set low when
the Data Register is updated. The
RDY pin and RDY bit will return high once the full contents of the register (either 16 or 24 bits)
have been read. If the Data Register has not been read by the time the next output update occurs, the
RDY pin and RDY bit will go
high for at least 158.5
× t
CLK IN indicating when a read from the Data Register should not be initiated to avoid a transfer from the
Data Register as it is being updated. Once the updating of the Data Register has taken place,
RDY returns low.
If the Communications Register data sets up the part for a write operation to this register, a write operation must actually take place
in order to return the part to where it is expecting a write operation to the Communications Register (the default state of the inter-
face). However, the 16 or 24 bits of data written to the part will be ignored by the AD7731.
Mode Register (RS2-RS0 = 0, 1, 0); Power-On/Reset Status: 0174 Hex
The Mode Register is a 16-bit register from which data can either be read or to which data can be written. This register configures
the operating modes of the AD7731, the input range selection, the channel selection and the word length of the Data Register. Table X
outlines the bit designations for the Mode Register. MR0 through MR15 indicate the bit location, MR denoting the bits are in the
Mode Register. MR15 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of
that bit. Figure 5 shows a flowchart for reading from the registers on the AD7731 and Figure 6 shows a flowchart for writing to the
registers on the part.
Table X. Mode Register
5
1
R
M4
1
R
M3
1
R
M2
1
R
M1
1
R
M0
1
R
M9
R
M8
R
M
)
0
(
2
D
M)
0
(
1
D
M)
0
(
0
D
M
B
)
0
(
U
/
)
0
(
N
E
D)
0
(
1
D)
0
(
0
D)
1
(
L
W
7
R
M6
R
M5
R
M4
R
M3
R
M2
R
M1
R
M0
R
M
)
0
(
F
E
R
I
H)
1
(
2
N
R)
1
(
1
N
R)
1
(
0
N
R)
0
(
O
B)
1
(
2
H
C)
0
(
1
H
C)
0
(
0
H
C
Bit
Location
Mnemonic
Description
MR15–MR13
MD2–MD0
Mode Bits. These three bits determine the mode of operation of the AD7731 as outlined in
Table XI. The modes are independent, such that writing new mode bits to the Mode Regis-
ter will exit the part from the mode in which it is operating and place it in the new requested
mode immediately after the Mode Register write. The function of the mode bits is described
in more detail below.
Table XI. Operating Modes
MD2
MD1
MD0
Mode of Operation
0
Sync (Idle) Mode
Power-On/Reset Default
0
1
Continuous Conversion Mode
0
1
0
Single Conversion Mode
0
1
Power-Down (Standby) Mode
1
0
Internal Zero-Scale Calibration
1
0
1
Internal Full-Scale Calibration
1
0
System Zero-Scale Calibration
1
System Full-Scale Calibration
REV. A
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