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参数资料
| 型号： | AD7746 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 温度/湿度传感器 |
| 英文描述： | DIGITAL TEMP SENSOR-SERIAL, 24BIT(s), 2Cel, RECTANGULAR, SURFACE MOUNT |
| 封装： | MO-153AB, TSSOP-16 |
| 文件页数： | 16/17页 |
| 文件大小： | 232K |
| 代理商： | AD7746 |
AD7745/AD7746
Preliminary Technical Data
Rev. PrF | Page 8 of 17
SERIAL INTERFACE
The AD7745/AD7746 supports an I2C compatible two wire
serial interface. The two wires on the I2C Bus are called SCL,
(clock) and SDA, (data). These two wires carry all addressing,
control and data information one bit at a time over the bus to all
connected peripheral devices. The SDA wire carries the data,
while the SCL wire synchronizes the sender and receiver during
the data transfer. I2C devices are classified as either a MASTER
or SLAVE devices. A device that initiates a data transfer message
is called a master, while a device that responds to this message is
called a slave.
To control the AD7745/AD7746 device on the bus the following
protocol must be followed. First, the master initiates a data
transfer by establishing a START CONDITION, defined by a
high-to-low transition on SDA while SCL remains high. This
indicates that the START BYTE will follow next. This 8 bit, start
byte is made up of a 7 bit address plus an R/W bit indicator.
All peripherals connected to the bus respond to the start condi-
tion and shift in the next eight bits (7-bit address + R/W bit).
The bits arrive MSB first. The peripheral that recognizes the
transmitted address responds by pulling the data line low dur-
ing
the
ninth
clock
pulse.
This
is
known
as
the
ACKNOWLEDGE bit. All other devices withdraw from the bus
at this point and maintain an IDLE CONDITION. An exception
to this is the GENERAL CALL address which is described later
in this document. The idle condition is where the device moni-
tors the SDA and SCL lines waiting for the start condition and
the correct address byte. The R/W bit determines the direction
of the data transfer. A logic ‘0’ LSB in the start byte means that
the master will write information to the addressed peripheral. In
this case the AD7745/AD7746 becomes a slave receiver. A logic
‘1’ LSB in the start byte means that the master will read infor-
mation from the addressed peripheral. In this case the
AD7745/AD7746 becomes a slave transmitter. In all instances,
the AD7745/AD7746 acts as a standard slave device on the I2C
bus.
The start byte address for the AD7745/AD7746 is 0x90 for a
Write and 0x91 for a Read.
WRITE OPERATION
When a WRITE is selected, the byte following the start byte is
always the register ADDRESS POINTER (sub-address) byte,
which points to of one of the internal registers on the
AD7745/AD7746. The address pointer byte is automatically
loaded into the address pointer register and acknowledged by
the AD7745/AD7746. After the address pointer byte acknowl-
edge,
a
STOP
CONDITION,
REPEATED
START
CONDITION, or another data byte can follow from the master.
A stop condition is defined by a low-to-high transition on SDA
while SCL remains high. If a stop condition is ever encountered
by the AD7745/AD7746, it will return to its idle condition and
the address pointer is reset to address 0x00.
If a data byte is transmitted after the register address pointer
byte, the AD7745/AD7746 will load this byte into the register
that is currently addressed by the address pointer register, send
an acknowledge and the address pointer auto-incrementer will
automatically increment the address pointer register to the next
internal register address. Thus subsequent transmitted data
bytes will be loaded into sequentially incremented addresses.
If a repeated start condition is encountered after the address
pointer byte, all peripherals connected to the bus respond ex-
actly as outlined above for a start condition, i.e. a repeated start
condition is treated the same as a start condition. (When a mas-
ter device issues a stop condition, it relinquishes control of the
bus, allowing another master device to take control of the bus.
Hence, a master wanting to retain control of the bus will issue
successive start conditions known as repeated start conditions).
READ OPERATION
When a READ is selected in the start byte, the register that is
currently addressed by the address pointer is transmitted on to
the SDA line by the AD7745/AD7746. This is then clocked out
by the master device and the AD7745/AD7746 will await an
acknowledge from the master.
If an acknowledge is received from the master, the address auto-
incrementer will automatically increment the address pointer
register and output the next addressed registers contents on to
the SDA line for transmission to the master. If no acknowledge
is received the AD7745/AD7746 returns to its idle state and the
address pointer is not incremented.
The address pointers’ auto-incrementer allows block data to be
written or read from the starting address and subsequent in-
cremental addresses. The user can also access any unique
register (address) on a one-to-one basis without having to up-
date all the registers. The address pointer register contents can-
not be read.
If an incorrect address pointer location is accessed or, if the user
allows the auto incrementer to exceed the required register ad-
dress, the following applies:
1.
In Read Mode, the AD7745/AD7746 will continue to out-
put various internal register contents until the master
device issues a not-acknowledge, start or stop condition.
The address pointers’ auto-incrementer’s contents will reset
to point to the STATUS REGISTER at address 0x00 when a
stop condition is received at the end of a read operation.
This allows the status register to be read (polled) continu-
ally without having to constantly write to address pointer.
2.
In Write Mode, the data for the invalid address will not be
loaded into the AD7745/AD7746 registers but an acknowl-
edge will be issued by the AD7745/AD7746.
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