参数资料
型号: AD7746ARUZ
厂商: Analog Devices Inc
文件页数: 5/28页
文件大小: 0K
描述: IC CONV 2CH CAP TO DGTL 16-TSSOP
设计资源: Extending the Capacitive Input Range of AD7745/AD7746 (CN0129)
标准包装: 96
类型: 电容数字转换器
分辨率(位): 24 b
数据接口: 串行
电压电源: 单电源
电源电压: 2.7 V ~ 5.25 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 16-TSSOP
包装: 管件
产品目录页面: 781 (CN2011-ZH PDF)
配用: EVAL-AD7746EBZ-ND - BOARD EVALUATION FOR AD7746
AD7745/AD7746
Rev. 0| Page 13 of 28
If a repeated start condition is encountered after the address
pointer byte, all peripherals connected to the bus respond
exactly as outlined above for a start condition, that is, a repeated
start condition is treated the same as a start condition. When a
master device issues a stop condition, it relinquishes control of
the bus, allowing another master device to take control of the
bus. Hence, a master wanting to retain control of the bus issues
successive start conditions known as repeated start conditions.
AD7745/AD7746 RESET
To reset the AD7745/AD7746 without having to reset the entire
I2C bus, an explicit reset command is provided. This uses a
particular address pointer word as a command word to reset the
part and upload all default settings. The AD7745/AD7746 do
not respond to the I2C bus commands (do not acknowledge)
during the default values upload for approximately 150 s
(max 200 s).
The reset command address word is 0xBF.
GENERAL CALL
When a master issues a slave address consisting of seven 0s with
the eighth bit (R/W bit) set to 0, this is known as the general call
address. The general call address is for addressing every device
connected to the I2C bus. The AD7745/AD7746 acknowledge
this address and read in the following data byte.
If the second byte is 0x06, the AD7745/AD7746 are reset,
completely uploading all default values. The AD7745/AD7746
do not respond to the I2C bus commands (do not acknowledge)
during the default values upload for approximately 150 s (max
200 s).
The AD7745/AD7746 do not acknowledge any other general
call commands.
1–7
8
9
1–7
8
9
1–7
8
9
P
S
START ADDR R/W ACK SUBADDRESS ACK
DATA
ACK
STOP
SDATA
SCLOCK
05468-006
Figure 24. Bus Data Transfer
DATA
A(S)
S
SLAVE ADDR A(S)
SUB ADDR
A(S)
LSB = 0
LSB = 1
DATA
P
S
SLAVE ADDR A(S)
SUB ADDR
A(S) S
SLAVE ADDR
A(S)
DATA
A(M)
DATA
P
WRITE
SEQUENCE
READ
SEQUENCE
A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = NO-ACKNOWLEDGE BY MASTER
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
S = START BIT
P = STOP BIT
A(S)
A(M)
05468-007
Figure 25. Write and Read Sequences
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