参数资料
型号: AD7765BRUZ
厂商: Analog Devices Inc
文件页数: 21/33页
文件大小: 0K
描述: IC ADC 24BIT S/D 156KSPS 28TSSOP
标准包装: 50
位数: 24
采样率(每秒): 156k
数据接口: 串行,SPI?
转换器数目: 1
功率耗散(最大): 371mW
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 28-TSSOP
包装: 管件
输入数目和类型: 1 个差分,单极;1 个差分,双极
产品目录页面: 779 (CN2011-ZH PDF)
AD7765
Rev. A | Page 27 of 32
USING THE AD7765
The following is the recommended sequence for powering up
and using the AD7765:
1. Apply power to the device.
2. Apply the MCLK signal.
3. Take RESET low for a minimum of one MCLK cycle,
preferably synchronous to the falling MCLK edge. If
multiple parts are to be synchronized, apply a common
4. Wait a minimum of two MCLK cycles after
RESET to all devices.
RESET
5. If multiple parts are being synchronized, a
has
been released.
SYNC pulse
must be applied to the parts, preferably synchronous with
the MCLK rising edge. In the case where devices are not
being synchronized, no SYNC pulse is required; a logic
high signal should simply be applied to the SYNC
When applying the
pin.
SYNC
The issue of a
pulse,
SYNC
Ensure that the
pulse to the device must not
coincide with a write to the device.
SYNC
Data can then be read from the device using the default gain
and overrange threshold values. The conversion data read is not
valid, however, until the settling time of the filter has elapsed.
Once this has occurred, the FILTER-SETTLE status bit is set,
indicating that the data is valid.
Values for gain and overrange thresholds can be written to or
read from the respective registers at this stage.
pulse is taken low for a
minimum of four MCLK periods.
BIAS RESISTOR SELECTION
The AD7765 requires a resistor to be connected between the
RBIAS and AGNDx pins. The resistor value should be selected to
give a current of 25 A through the resistor to ground. For a
4.096 V reference voltage, the correct resistor value is 160 k.
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