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参数资料
| 型号： | AD7778ASZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/12页 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 8CHAN HS 44-MQFP |
| 标准包装： | 1 |
| 位数： | 10 |
| 采样率（每秒）： | 378k |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-QFP |
| 供应商设备封装： | 44-MQFP（10x10） |
| 包装： | 托盘 |
| 输入数目和类型： | 8 个单端，单极 |
AD7776/AD7777/AD7778
–7–
REV. A
ADC Conversion Start Timing
Figure 6 shows the operating waveforms for the start of a conver-
sion cycle. On the rising edge of
WR, the conversion cycle starts
with the acquisition and tracking of the selected ADC channel,
AIN1–8. The analog input voltage is held 40 ns (typically) after
the first rising edge of CLKIN following four complete CLKIN
cycles. If tD in Figure 6 is greater than 12 ns, the falling edge of
CLKIN as shown is seen as the first falling clock edge. If tD is
less than 12 ns, the first falling clock edge to be recognized does
not occur until one cycle later.
Following the “hold” on the analog input(s), two complete
CLKIN cycles are allowed for settling purposes before the MSB
decision is made. The actual decision point occurs approximately
40 ns after the rising edge of CLKIN as shown in Figure 6. Two
more CLKIN cycles are allowed for the second MSB decision.
The succeeding bit decisions are made approximately 40 ns
after each rising edge of CLKIN until the conversion is complete.
At the end of conversion, if a single conversion has been
requested (CR6 = 0), the
BUSY/INT line changes state (as
programmed by CR9) and the SAR contents are transferred to
the first register ADCREG1. The SAR is then reset in readiness for
a new conversion. If simultaneous sampling has been requested
(CR6 = 1), no change occurs in the status of the
BUSY/INT
output, and the ADC automatically starts the second conversion.
At the end of this conversion, the
BUSY/INT line changes state
(as programmed by CR9) and the SAR contents are transferred
to the second register, ADCREG2.
tD*
CLKIN
VIN
WR
CHANNEL ACQUISITION
40ns
TYP
40ns
TYP
'HOLD'
DB9 (MSB)
* TIMING SHOWN FOR tD GREATER THAN 12ns
Figure 6. ADC Conversion Start Timing
Track-and-Hold
The track-and-hold (T/H) amplifiers on the analog input(s) of
the AD7776/AD7777/AD7778 allow the ADC to accurately
convert an input sine wave of 2 V peak-peak amplitude up to a
frequency of 189 kHz, the Nyquist frequency of the ADC when
operated at its maximum throughput rate of 378 kHz. This
maximum rate of conversion includes conversion time and the
time between conversions. Because the input bandwidth of the
track-and-hold is much greater than 189 kHz, the input signal
should be band limited to avoid folding unwanted signals into
the band of interest.
Power-Down
The AD7776/AD7777/AD7778 can be placed in a power-down
mode simply by writing a logic high to location CR8 of the
control register. The following changes are effected immediately
upon writing a “1” to location CR8:
Any conversion in progress is terminated.
If a conversion is in progress, the leading edge of WR immedi-
ately drives the
BUSY/INT output high.
All the linear circuitry is turned off.
The REFOUT output stops being driven and is weakly (5 k)
pulled to analog ground.
Control inputs
CS, WR, and RD retain their purpose while the
AD7776/AD7777/AD7778 is in power-down mode. If no
conversions are in progress when the AD7776/AD7777/AD7778
is placed into power-down mode, the contents of the ADC
registers, ADCREG1 and ADCREG2, are retained during
power-down and can be read as normal. On returning to normal
operating mode, a new conversion (or conversions, dependent
on CR6) is automatically started. Upon completion, the invalid
conversion results are loaded into the ADC registers, losing the
previous valid results.
To achieve the lowest possible power consumption in the
power-down mode, special attention must be paid to the state of
the digital and analog inputs and outputs:
Because each analog input channel sees a resistive divider to
AGND, the input resistance of which does not change
between normal and power-down modes, driving the analog
input signals to 0 V or as close as possible to 0 V minimizes
the power dissipated in the input signal conditioning circuitry.
Similarly, the REFIN input sees a resistive divider to AGND,
the input resistance of which does not change between
normal and power-down modes. If an external reference is
being used, then driving this reference input to 0 V or as
close as possible to 0 V minimizes the power dissipated in
the input signal conditioning circuitry.
Since the REFOUT pin is pulled to AGND via, typically, a
5 k
resistor, any voltage above 0 V that this output may be
pulled to by external circuitry dissipates unnecessary power.
Digital inputs CS, WR, and RD should all be held at V
CC or
as close as possible. CLKIN should be held as close as
possible to either 0 V or VCC.
Since the BUSY/INT output is actively driven to a logic high,
any loading on this pin to 0 V dissipates power.
The AD7776/AD7777/AD7778 comes out of the power-down
mode when a Logic “0” is written to location CR8 of the
control register. Note that the contents of the other locations
in the control register are retained when the device is placed in
power-down and are valid when power is restored. However,
coming out of power-down provides an opportunity to reload
the complete contents of the control register without any
extra instructions.
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