参数资料
| 型号： | AD7791BRM |
| 厂商： | Analog Devices Inc |
| 文件页数： | 19/20页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT BUFFERED LP 10MSOP |
| 标准包装： | 50 |
| 位数： | 24 |
| 采样率（每秒）： | 120 |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 230µW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 10-MSOP |
| 包装： | 管件 |
| 输入数目和类型： | 1 个差分，单极；1 个差分，双极 |
AD7791
Data Sheet
Rev. A | Page 8 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
04227-0-005
AD7791
TOP VIEW
(Not to Scale)
SCLK
1
CS
2
AIN(+)
3
AIN(–)
4
REF(+)
5
DIN
DOUT/RDY
VDD
GND
REF(–)
10
9
8
7
6
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin
No.
Mnemonic
Function
1
SCLK
Serial Clock Input for Data Transfers to and
from the ADC. The SCLK has a Schmitt-
triggered input, making the interface suita-
ble for opto-isolated applications. The serial
clock can be continuous with all data
transmitted in a continuous train of pulses.
Alternatively, it can be a noncontinuous
clock with the information being trans-
mitted to or from the ADC in smaller
batches of data.
2
CS
Chip Select Input. This is an active low logic
input used to select the ADC. CS can be
used to select the ADC in systems with
more than one device on the serial bus or as
a frame synchronization signal in communi-
cating with the device. CS can be hardwired
low, allowing the ADC to operate in 3-wire
mode with SCLK, DIN, and DOUT used to
interface with the device.
3
AIN(+)
Analog Input. AIN(+) is the positive terminal
of the fully differential analog input.
4
AIN(–)
Analog Input. AIN(–) is the negative termi-
nal of the fully differential analog input.
5
REFIN(+)
Positive Reference Input. REFIN(+) can lie
anywhere between VDD and GND + 0.1 V.
The nominal reference voltage (REFIN(+) –
REFIN(–)) is 2.5 V, but the part functions with
a reference from 0.1 V to VDD.
Pin
No.
Mnemonic
Function
6
REFIN(–)
Negative Reference Input. This reference
input can lie anywhere between GND and
VDD – 0.1 V.
7
GND
Ground Reference Point.
8
VDD
Supply Voltage, 2.5 V to 5.25 V.
9
DOUT/RDY
Serial Data Output/Data Ready Output.
DOUT/RDY serves a dual purpose . It functions
as a serial data output pin to access the output
shift register of the ADC. The output shift reg-
ister can contain data from any of the
on-chip data or control registers. In addition,
DOUT/RDY operates as a data ready pin,
going low to indicate the completion of a
conversion. If the data is not read after the
conversion, the pin will go high before the
next update occurs.
The DOUT/RDY falling edge can be used as an
interrupt to a processor, indicating that valid
data is available. With an external serial clock,
the data can be read using the DOUT/RDY pin.
With CS low, the data/control word informa-
tion is placed on the DOUT/RDY pin on the
SCLK falling edge and is valid on the SCLK
rising edge.
The end of a conversion is also indicated by
the RDY bit in the status register. When CS is
high, the DOUT/RDY pin is three-stated but
the RDY bit remains active.
10
DIN
Serial Data Input to the Input Shift Register
on the ADC. Data in this shift register is trans-
ferred to the control registers within
the ADC, the register selection bits of the
communications register identifying the
appropriate register.
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