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参数资料
| 型号： | AD7792BRU |
| 厂商： | Analog Devices Inc |
| 文件页数： | 20/33页 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT 3CH LP 16-TSSOP |
| 标准包装： | 96 |
| 位数： | 16 |
| 采样率（每秒）： | 500 |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 2.5mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 管件 |
| 输入数目和类型： | 3 个差分，单极；3 个差分，双极 |
| 配用： | EVAL-AD7792EBZ-ND - BOARD EVALUATION FOR AD7792 |
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AD7792/AD7793
Rev. B | Page 26 of 32
AVDD MONITOR
Along with converting external voltages, the ADC can be used
to monitor the voltage on the AVDD pin. When Bit CH2 to
Bit CH0 equal 1, the voltage on the AVDD pin is internally
attenuated by 6, and the resultant voltage is applied to the ∑-Δ
modulator using an internal 1.17 V reference for analog-to-
digital conversion. This is useful, because variations in the
power supply voltage can be monitored.
CALIBRATION
The AD7792/AD7793 provide four calibration modes that can
be programmed via the mode bits in the mode register. These
are internal zero-scale calibration, internal full-scale calibration,
system zero-scale calibration, and system full-scale calibration,
which effectively reduces the offset error and full-scale error to
the order of the noise. After each conversion, the ADC con-
version result is scaled using the ADC calibration registers
before being written to the data register. The offset calibration
coefficient is subtracted from the result prior to multiplication
by the full-scale coefficient.
To start a calibration, write the relevant value to the MD2 to
MD0 bits in the mode register. After the calibration is complete,
the contents of the corresponding calibration registers are
updated, the RDY bit in the status register is set, the DOUT/
RDY pin goes low (if CS is low), and the AD7792/AD7793
revert to idle mode.
During an internal zero-scale or full-scale calibration, the
respective zero input and full-scale input are automatically
connected internally to the ADC input pins. A system
calibration, however, expects the system zero-scale and system
full-scale voltages to be applied to the ADC pins before the
calibration mode is initiated. In this way, external ADC errors
are removed.
From an operational point of view, a calibration should be
treated like another ADC conversion. A zero-scale calibration
(if required) should always be performed before a full-scale
calibration. System software should monitor the RDY bit in
the status register or the DOUT/RDY pin to determine the
end of calibration via a polling sequence or an interrupt-driven
routine.
Both an internal offset calibration and a system offset
calibration take two conversion cycles. An internal offset
calibration is not needed, as the ADC itself removes the offset
continuously.
To perform an internal full-scale calibration, a full-scale input
voltage is automatically connected to the selected analog input
for this calibration. When the gain equals 1, a calibration takes
2 conversion cycles to complete. For higher gains, 4 conversion
cycles are required to perform the full-scale calibration.
DOUT/RDY goes high when the calibration is initiated and
returns low when the calibration is complete.
The ADC is placed in idle mode following a calibration. The
measured full-scale coefficient is placed in the full-scale register
of the selected channel. Internal full-scale calibrations cannot be
performed when the gain equals 128. With this gain setting, a
system full-scale calibration can be performed. A full-scale
calibration is required each time the gain of a channel is
changed to minimize the full-scale error.
An internal full-scale calibration can be performed at specified
update rates only. For gains of 1, 2, and 4, an internal full-scale
calibration can be performed at any update rate. However, for
higher gains, internal full-scale calibrations can be performed
when the update rate is less than or equal to 16.7 Hz, 33.2 Hz,
and 50 Hz only. However, the full-scale error does not vary with
update rate, so a calibration at one update rate is valid for all
update rates (assuming the gain or reference source is not
changed).
A system full-scale calibration takes 2 conversion cycles to
complete, irrespective of the gain setting. A system full-scale
calibration can be performed at all gains and all update rates. If
system offset calibrations are being performed along with
system full-scale calibrations, the offset calibration should be
performed before the system full-scale calibration is initiated.
GROUNDING AND LAYOUT
Because the analog inputs and reference inputs of the ADC are
differential, most of the voltages in the analog modulator are
common-mode voltages. The excellent common-mode reject-
ion of the part removes common-mode noise on these inputs.
The digital filter provides rejection of broadband noise on the
power supply, except at integer multiples of the modulator
sampling frequency. The digital filter also removes noise from
the analog and reference inputs, provided that these noise
sources do not saturate the analog modulator. As a result, the
AD7792/AD7793 are more immune to noise interference than a
conventional high resolution converter. However, because the
resolution of the AD7792/AD7793 is so high, and the noise
levels from the AD7792/AD7793 are so low, care must be taken
with regard to grounding and layout.
The printed circuit board that houses the AD7792/AD7793
should be designed such that the analog and digital sections are
separated and confined to certain areas of the board. A mini-
mum etch technique is generally best for ground planes because
it provides the best shielding.
It is recommended that the GND pins of the AD7792/AD7793
be tied to the AGND plane of the system. In any layout, it is
important to keep in mind the flow of currents in the system,
ensuring that the return paths for all currents are as close as
possible to the paths the currents took to reach their destinations.
Avoid forcing digital currents to flow through the AGND
sections of the layout.
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