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| 型号： | AD7798BRUZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 6/28页 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT SIG-DEL 3CH 16TSSOP |
| 标准包装： | 96 |
| 位数： | 16 |
| 采样率（每秒）： | 470 |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 2mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 管件 |
| 输入数目和类型： | 3 个差分，单极；3 个差分，双极 |
| 产品目录页面： | 779 (CN2011-ZH PDF) |
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AD7798/AD7799
Data Sheet
Rev. B | Page 14 of 28
STATUS REGISTER
RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80 (AD7798)/0x88 (AD7799)
The status register is an 8-bit, read-only register. To access the status register, the user must write to the communication register, select the
next operation to be a read, and load Bit RS2, Bit RS1, and Bit RS0 with 0. Table 11 outlines the bit designations for the status register. SR0
through SR7 indicate the bit locations, with SR denoting that the bits are in the status register. SR7 denotes the first bit of the data stream.
The number in parentheses indicates the power-on/reset default status of the bit.
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
RDY(1)
ERR(0)
NOREF(0)
0(0)
0/1
CH2(0)
CH1(0)
CH0(0)
Table 11. Status Register Bit Designations
Bit Location
Bit Name
Description
SR7
RDY
Ready Bit. Cleared when data is written to the data register. Set after the data register is read or after a period
of time before the data register is updated with a new conversion result to indicate to the user not to read the
conversion data. It is also set when the part is placed in power-down mode. The end of a conversion is
indicated by the DOUT/RDY pin. This pin can be used as an alternative to the status register for monitoring
the ADC for conversion data.
SR6
ERR
Error Bit. This bit is written to at the same time as the RDY bit. Set to indicate that the result written to the
data register is clamped to all 0s or all 1s. Error sources include overrange and underrange. Cleared by a write
operation to start a conversion.
SR5
NOREF
No Reference Bit. Set to indicate that the reference (REFIN) is at a voltage below a specified threshold. When
NOREF is set, conversion results are clamped to all 1s. Cleared to indicate that a valid reference is applied to
the reference pins. The NOREF bit is enabled by setting the REF_DET bit in the configuration register to 1.
SR4
0
This bit is automatically cleared.
SR3
0/1
This bit is automatically cleared on the AD7798 and automatically set on the AD7799.
SR2 to SR0
CH2 to CH0
These bits indicate which channel is being converted by the ADC.
MODE REGISTER
RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x000A
The mode register is a 16-bit register from which data can be read or to which data can be written. This register is used to select the
operating mode, update rate, and low-side power switch. Table 12 outlines the bit designations for the mode register. MR0 through MR15
indicate the bit locations, with MR denoting that the bits are in the mode register. MR15 denotes the first bit of the data stream. The
number in parentheses indicates the power-on/reset default status of that bit. A write to the mode register resets the modulator and filter
and sets the RDY bit.
MR15
MR14
MR13
MR12
MR11
MR10
MR9
MR8
MD2(0)
MD1(0)
MD0(0)
PSW(0)
0(0)
MR7
MR6
MR5
MR4
MR3
MR2
MR1
MR0
0(0)
FS3(1)
FS2(0)
FS1(1)
FS0(0)
Table 12. Mode Register Bit Designations
Bit Location
Bit Name
Description
MR15 to MR13
MD2 to MD0
Mode Select Bits. These bits select the operational mode of the AD7798/AD7799 (see Table 13).
MR12
PSW
Power Switch Control Bit. Set by user to close the power switch PSW to GND. The power switch can
sink up to 30 mA. Cleared by user to open the power switch. When the ADC is placed in power-down
mode, the power switch is opened.
MR11 to MR4
0
These bits must be programmed with a Logic 0 for correct operation.
MR3 to MR0
FS3 to FS0
Filter Update Rate Select Bits (see Table 14).
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