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参数资料
| 型号： | AD7801BRU-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/16页 |
| 文件大小： | 0K |
| 描述： | IC DAC 8BIT PARALLEL INP 20TSSOP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 标准包装： | 1,000 |
| 设置时间： | 1.2µs |
| 位数： | 8 |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 12.9mW |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 1 电压，单极；1 电压，双极 |
| 采样率（每秒）： | 833k |
AD7801
–8–
REV. 0
Reference
The AD7801 has the ability to use either an external reference
applied through the REFIN pin or an internal reference generated
from VDD. Figure 20 shows the reference input arrangement
where either the internal VDD/2 or the externally applied reference
can be selected.
The internal reference is selected by tying the REFIN pin to
VDD. If an external reference is to be used, this can be directly
applied to the REFIN pin and if this is 1 V below VDD, the
internal circuitry will select this externally applied reference as
the reference source for the DAC.
Digital Interface
The AD7801 contains a fast parallel interface allowing this
DAC to interface to industry standard microprocessors,
microcontrollers and DSP machines. There are two modes in
which this parallel interface can be configured to update the
DAC output. The synchronous update mode allows synchro-
nous updating of the DAC output; the automatic update mode
allows the DAC to be updated individually following a write
cycle. Figure 21 shows the internal logic associated with the
digital interface. The PON STRB signal is internally generated
from the power-on reset circuitry and is low during the power-
on reset phase of the power up procedure.
CLEAR
SET SLE
LDAC
ENABLE
DAC CONTROL
LOGIC
MLE
SLE
CLR
PON STRB
CLR
LDAC
CS
WR
Figure 21. Logic Interface
The AD7801 has a double buffered interface, which allows for
synchronous updating of the DAC output. Figure 22 shows a
block diagram of the register arrangement within the AD7801.
MLE
SLE
CONTROL LOGIC
CS
WR
LDAC
CLR
4
15
30
8
INPUT
REGISTER
4
TO
15
DECODER
DAC
REGISTER
4
15
30
4
TO
15
DECODER
DAC
REGISTER
DRIVERS
LOWER
NIBBLE
UPPER
NIBBLE
DB7-DB0
DRIVERS
Figure 22. Register Arrangement
Automatic Update Mode
In this mode of operation the
LDAC signal is permanently tied
low. The state of the
LDAC is sampled on the rising edge of
WR. LDAC being low allows the DAC register to be automati-
cally updated on the rising edge of
WR. The output update
occurs on the rising edge of
WR. Figure 23 shows the timing
associated with the automatic update mode of operation and
also the status of the various registers during this frame.
HOLD
TRACK
D7-D0
WR
CS
LDAC = 0
I/P REG (MLE)
DAC REG (SLE)
VOUT
TRACK
HOLD
Figure 23. Timing and Register Arrangement for Auto-
matic Update Mode
Synchronous Update Mode
In this mode of operation the
LDAC signal is used to update the
DAC output to synchronize with other updates in the system.
The state of the
LDAC is sampled on the rising edge of WR. If
LDAC is high, the automatic update mode is disabled and the
DAC latch is updated at any time after the write by taking
LDAC low. The output update occurs on the falling edge of
LDAC. LDAC must be taken back high again before the next
data transfer takes place. Figure 24 shows the timing associated
with the synchronous update mode of operation and also the
status of the various registers during this frame.
HOLD
D7-D0
WR
CS
LDAC
I/P REG (MLE)
DAC REG (SLE)
VOUT
HOLD
TRACK
Figure 24. Timing and Register Arrangement for Synchro-
nous Update Mode
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