参数资料
型号: AD7810YRZ-REEL
厂商: Analog Devices Inc
文件页数: 10/11页
文件大小: 0K
描述: IC ADC 10BIT SRL HS LP 8SOIC
标准包装: 2,500
位数: 10
采样率(每秒): 350k
数据接口: 串行
转换器数目: 1
功率耗散(最大): 17.5mW
电压电源: 单电源
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 带卷 (TR)
输入数目和类型: 2 个伪差分,单极
AD7810
–8–
REV. B
POWER-UP TIMES
The AD7810 has a 1.5
s power-up time. When VDD is first
connected, the AD7810 is in a low current mode of operation.
In order to carry out a conversion, the AD7810 must first be
powered up. The ADC is powered up by a rising edge on the
CONVST pin. A conversion is initiated on the falling edge of
CONVST. Figure 12 shows how to power up the AD7810 when
VDD is first connected or after the AD7810 is powered down
using the CONVST pin.
Care must be taken to ensure that the CONVST pin of the
AD7810 is logic low when VDD is first applied.
MODE 1 (
CONVST IDLES HIGH)
VDD
MODE 2 (
CONVST IDLES LOW)
VDD
< 1 s
t
POWER-UP
1.5 s
t
POWER-UP
1.5 s
CONVST
Figure 12. Power-Up Times
POWER VS. THROUGHPUT RATE
By operating the AD7810 in Mode 2, the average power con-
sumption of the AD7810 decreases at lower throughput rates.
Figure 13 shows how the automatic power-down is implemented
using the CONVST signal to achieve the optimum power per-
formance for the AD7810. As the throughput rate is reduced, the
device remains in its power-down state longer and the average
power consumption over time drops accordingly.
tCYCLE
100 s @ 10kSPS
CONVST
tCONVERT
2.3 s
POWER-DOWN
tPOWER-UP
1.5 s
Figure 13. Automatic Power-Down
For example, if the AD7810 is operated in a continuous sampling
mode with a throughput rate of 10 kSPS, the power consump-
tion is calculated as follows. The power dissipation during normal
operation is 9 mW, VDD = 3 V. If the power-up time is 1.5
s
and the conversion time is 2.3
s, the AD7810 can be said to
dissipate 9 mW for 3.8
s (worst case) during each conversion
cycle. If the throughput rate is 10 kSPS, the cycle time is
100
s and the average power dissipated during each cycle is
(3.8/100)
× (9 mW) = 342 W. Figure 2 shows a graph of
Power vs. Throughput.
OPERATING MODES
Mode 1 Operation (High Speed Sampling)
When the AD7810 is used in this mode of operation, the part is
not powered down between conversions. This mode of opera-
tion allows high throughput rates to be achieved. The timing
diagram in Figure 14 shows how this optimum throughput rate
is achieved by bringing the CONVST signal high before the end
of the conversion. The AD7810 leaves its tracking mode and
goes into hold on the falling edge of CONVST. A conversion is
also initiated at this time. The conversion takes 2.3
s to complete.
At this point, the result of the current conversion is latched into the
serial shift register, and the state of the CONVST signal checked.
The CONVST signal should be high at the end of the conversion
to prevent the part from powering down.
A
B
t2
DOUT
CURRENT CONVERSION RESULT
t1
SCLK
CONVST
Figure 14. Mode 1 Operation Timing
The serial port on the AD7810 is enabled on the rising edge of
the CONVST signal (see Serial Interface section). As explained
earlier, this rising edge should occur before the end of the con-
version process if the part is not to be powered down. A serial
read can take place at any stage after the rising edge of CONVST.
If a serial read is initiated before the end of the current con-
version process (i.e., at time “A”), the result of the previous
conversion is shifted out on the DOUT pin. It is possible to allow
the serial read to extend beyond the end of a conversion. In this
case the new data will not be latched into the output shift regis-
ter until the read has finished. The dynamic performance of the
AD7810 typically degrades by up to 3 dBs while reading during
a conversion. If the user waits until the end of the conversion
process, i.e., 2.3
s after falling edge of CONVST (Point “B”),
before initiating a read, the current conversion result is shifted out.
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