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参数资料
| 型号： | AD7812YNZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 18/24页 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 8CHAN SRL 20DIP |
| 标准包装： | 18 |
| 位数： | 10 |
| 采样率（每秒）： | 350k |
| 数据接口： | DSP，串行 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 10.5mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 20-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 20-PDIP |
| 包装： | 管件 |
| 输入数目和类型： | 8 个单端，单极；7 伪差分，单极 |
–3–
REV.
C
AD7811/AD7812
Parameter
Y Version
Unit
Test Conditions/Comments
POWER SUPPLY
VDD
2.7
V min
For Specified Performance
5.5
V max
IDD
Digital Inputs = 0 V or VDD
Normal Operation
3.5
mA max
Power-Down
Full Power-Down
1
A max
Partial Power-Down (Internal Ref)
350
A max
Power Dissipation
VDD = 3 V
Normal Operation
10.5
mW max
Auto Full Power-Down
Throughput 1 kSPS
31.5
W max
Throughput 10 kSPS
315
W max
Throughput 100 kSPS
3.15
mW max
Partial Power-Down (Internal Ref)
1.05
mW max
Full Power-Down
3
W max
NOTES
1See Terminology.
2Sample tested during initial release and after any redesign or process change that may affect this parameter.
Specifications subject to change without notice.
TIMING CHARACTERISTICS1, 2
Parameter
Y Version
Unit
Conditions/Comments
t
POWER-UP
1.5
s (max)
Power-Up Time of AD7811/AD7812 after Rising Edge of
CONVST
t
1
2.3
s (max)
Conversion Time
t
2
20
ns (min)
CONVST Pulsewidth
t
3
25
ns (min)
SCLK High Pulsewidth
t
4
25
ns (min)
SCLK Low Pulsewidth
t
5
ns (min)
RFS Rising Edge to SCLK Rising Edge Setup Time
t
6
5
ns (min)
TFS Falling Edge to SCLK Falling Edge Setup Time
t
7
10
ns (max)
SCLK Rising Edge to Data Out Valid
t
8
10
ns (min)
DIN Data Valid to SCLK Falling Edge Setup Time
t
9
5
ns (min)
DIN Data Valid after SCLK Falling Edge Hold Time
t
10
20
ns (max)
SCLK Rising Edge to DOUT High Impedance
t
11
100
ns (min)
DOUT High Impedance to
CONVST Falling Edge
NOTES
1Sample tested to ensure compliance.
2See Figures 16, 17 and 18.
3These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for V
DD = 5 V
± 10% and
0.4 V or 2 V for VDD = 3 V
± 10%.
4Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 11, quoted in the Timing Characteristics is the true bus relinquish
time of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
(VDD = 2.7 V to 5.5 V, VREF = VDD [EXT] unless otherwise noted)
2.1V
200 A
CL
50pF
IOH
TO
OUTPUT
PIN
IOL
200 A
Figure 1. Load Circuit for Digital Output Timing Specifications
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