- 您现在的位置：买卖IC网 > PDF目录10184 > AD7854ARZ (Analog Devices Inc)IC ADC 12BIT PARALLEL LP 28SOIC PDF资料下载
参数资料
| 型号： | AD7854ARZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 17/28页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT PARALLEL LP 28SOIC |
| 标准包装： | 27 |
| 位数： | 12 |
| 采样率（每秒）： | 200k |
| 数据接口： | 并联 |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 30mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC W |
| 包装： | 管件 |
| 输入数目和类型： | 1 个伪差分，单极；1 个伪差分，双极 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页当前第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页
AD7854/AD7854L
–24–
REV. B
MICROPROCESSOR INTERFACING
The parallel port on the AD7854/AD7854L allows the device to
be interfaced to microprocessors or DSP processors as a memory
mapped or I/O mapped device. The
CS and RD inputs are
common to all memory peripheral interfacing. Typical inter-
faces to different processors are shown in Figures 38 to 41.
In all the interfaces shown, an external timer controls the
CONVST input of the AD7854/AD7854L and the BUSY out-
put interrupts the host DSP. Also, the HBEN pin is connected
to address line A0 (XA0 in the case of the TMS320C30). This
maps the AD7854/AD7854L to two locations in the processor
memory space, ADCaddr and ADCaddr+1. Thus when writing
to the ADC, first the 8 LSBs of the 16-bit are written to address
location ADCaddr and then the 8 MSBs to location ADCaddr+1.
All the interfaces use a 12-bit data bus, so only one read is needed
from location ADCaddr to access the ADC output data register
or the status register. To read from the other registers, the
8 MSBs must be read from location ADCaddr+1. Interfacing
to 8-bit bus systems is similar, except that two reads are
required to obtain data from all the registers.
AD7854/AD7854L to ADSP-21xx
Figure 38 shows the AD7854/AD7854L interfaced to the
ADSP-21xx series of DSPs as a memory mapped device. A
single wait state may be necessary to interface the AD7854/
AD7854L to the ADSP-21xx depending on the clock speed of
the DSP. This wait state can be programmed via the data
memory waitstate control register of the ADSP-21xx (please see
ADSP-2100 Family Users Manual for details). The following
instruction reads data from the AD7854/AD7854L:
AX 0 = DM(ADCaddr)
Data can be written to the AD7854/AD7854L using the
instructions:
DM (ADCaddr) = AY 0
DM (ADCaddr+1) = AY 1
where ADCaddr is the address of the AD7854/AD7854L in
ADSP-21xx data memory, AX 0 contains the data read from the
ADC, and AY 0 contains the 8 LSBs and AY 1 the 8 MSBs of
data written to the AD7854/AD7854L.
ADSP-21xx*
A13–A1
DMS
A0
WR
IRQ2
D23–D8
CS
HBEN
WR
RD
BUSY
DB11–DB0
AD7854/
AD7854L*
ADDR
DECODE
EN
ADDRESS BUS
DATA BUS
*ADDITIONAL PINS OMITTED FOR CLARITY
RD
Figure 38. AD7854/AD7854L to ADSP-21xx Parallel Interface
AD7854/AD7854L to TMS32020, TMS320C25 and TMS320C5x
A parallel interface between the AD7854/AD7854L and the
TMS32020, TMS320C25 and TMS320C5x family of DSPs are
shown in Figure 39. The memory mapped addresses chosen for
the AD7854/AD7854L should be chosen to fall in the I/O
memory space of the DSPs.
The parallel interface on the AD7854/AD7854L is fast enough
to interface to the TMS32020 with no extra wait states. In the
TMS320C25 interface, data accesses may be slowed sufficiently
when reading from and writing to the part to require the inser-
tion of one wait state. In such a case, this wait state can be
generated using the single OR gate to combine the
CS and
MSC signals to drive the READY line of the TMS320C25, as
shown in Figure 39. Extra wait states are necessary when using
the TMS320C5x at their fastest clock speeds. Wait states can
be programmed via the IOWSR and CWSR registers (please see
TMS320C5x User Guide for details).
Data is read from the ADC using the following instruction:
IN D,ADCaddr
where D is the memory location where the data is to be stored
and ADCaddr is the I/O address of the AD7854/AD7854L.
Data is written to the ADC using the following two instructions:
OUT D8LSB, ADCaddr
OUT D8MSB, ADCaddr+1
where D8LSB is the memory location where the 8 LSBs of data
are stored, D8MSB is the location where the 8 MSBs of data are
stored and ADCaddr and ADCaddr+1 are the I/O memory
spaces that the AD7854/AD7854L is mapped into.
TMS32020/
TMS320C25/
TMS320C50*
A15–A1
IS
READY
MSC
A0
STRB
R/
W
INTx
D23–D0
TMS320C25
ONLY
CS
HBEN
WR
RD
BUSY
DB11–DB0
AD7854/
AD7854L*
ADDR
DECODE
EN
ADDRESS BUS
DATA BUS
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 39. AD7854/AD7854L to TMS32020/C25/C5x
Parallel Interface
相关PDF资料 |
PDF描述 |
|---|---|
| VI-B62-IV-S | CONVERTER MOD DC/DC 15V 150W |
| PT02A-16-26P | CONN RECEPT 26POS W/PINS SOLDER |
| MS3120F12-10S | CONN RCPT 10POS WALL MNT W/SCKT |
| AD7854AR | IC ADC 12BIT PARALLEL LP 28-SOIC |
| ADM3312EARUZ-REEL | IC TXRX RS-232 3:3 2.7V 24TSSOP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD7854ARZ-REEL | 功能描述:IC ADC 12BIT PARALLEL LP 28SOIC RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:12 采样率（每秒）:300k 数据接口:并联 转换器数目:1 功率耗散（最大）:75mW 电压电源:单电源 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC 包装:带卷 (TR) 输入数目和类型:1 个单端，单极；1 个单端，双极 |
| AD7854BR | 制造商:Analog Devices 功能描述:ADC Single SAR 200ksps 12-bit Parallel 28-Pin SOIC W 制造商:Rochester Electronics LLC 功能描述:12-BIT SINGLE CH.PARALLEL ADC I.C. - Bulk |
| AD7854BR-REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 200ksps 12-bit Parallel 28-Pin SOIC W T/R |
| AD7854BRZ | 功能描述:IC ADC 12BIT PARALLEL LP 28-SOIC RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:12 采样率（每秒）:3M 数据接口:- 转换器数目:- 功率耗散（最大）:- 电压电源:- 工作温度:- 安装类型:表面贴装 封装/外壳:SOT-23-6 供应商设备封装:SOT-23-6 包装:带卷 (TR) 输入数目和类型:- |
| AD7854L | 制造商:AD 制造商全称:Analog Devices 功能描述:3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs |
发布紧急采购，3分钟左右您将得到回复。