参数资料
型号: AD7862ARSZ-10REEL
厂商: Analog Devices Inc
文件页数: 16/16页
文件大小: 0K
描述: IC ADC 12BIT DUAL 250KSPS 28SSOP
标准包装: 1,500
位数: 12
采样率(每秒): 250k
数据接口: 并联
转换器数目: 2
功率耗散(最大): 75mW
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-SSOP(0.209",5.30mm 宽)
供应商设备封装: 28-SSOP
包装: 带卷 (TR)
输入数目和类型: 4 个单端,双极
AD7862
–9–
REV. 0
and fourth read pulses, after the second conversion and A0 high,
access the result from Channel B (VB1 and VB2 respectively). A0’s
state can be changed any time after the CONVST goes high,
i.e., track/holds into hold, and 400 ns prior to the next falling
edge of CONVST. Data is read from the part via a 12-bit
parallel data bus with standard CS and RD signal, i.e., the read
operation consists of a negative going pulse on the CS pin
combined with two negative going pulses on the RD pin (while
the CS is low), accessing the two 12-bit results. Once the read
operation has taken place, a further 300 ns should be allowed
before the next falling edge of CONVST to optimize the settling
of the track/hold amplifier before the next conversion is initiated.
With the internal clock frequency at its maximum (3.7 MHz—not
accessible externally), the achievable throughput rate for the
part is 3.6
s (conversion time) plus 100 ns (read time) plus
0.3
s (acquisition time). This results in a minimum throughput
time of 4
s (equivalent to a throughput rate of 250 kHz).
Read Options
Apart from the read operation described above and displayed in
Figure 5a, other CS and RD combinations can result in
different channels/inputs being read in different combinations.
Suitable combinations are shown in Figures 5b through 5d.
VA1
VA2
CS
RD
DATA
Figure 5b. Read Option A
VA1
VA2
CS
RD
DATA
VA1
Figure 5c. Read Option B
VA1
VB1
A0
CS
RD
DATA
Figure 5d. Read Option C
OPERATING MODES
Mode 1 Operation (High Sampling Performance)
The timing diagram in Figure 5a is for optimum performance in
operating mode 1 where the falling edge of CONVST starts
conversion and puts the track/hold amplifiers into their hold
mode. This falling edge of CONVST also causes the BUSY
signal to go high to indicate that a conversion is taking place.
The BUSY signal goes low when the conversion is complete,
which is 3.6
s max after the falling edge of CONVST, and new
data from this conversion is available in the output latch of the
AD7862. A read operation accesses this data. If the multiplexer
select A0 is low, the first and second read pulses after the first
conversion access the result from Channel A (VA1 and VA2
VA1
VA2
VB1
VB2
t
3
t
1
t
2
t
4
t
5
t
6
t
CONV = 3.6s
t7
CONVST
BUSY
A0
CS
RD
DATA
300ns
400ns
Figure 5a. Mode 1 Timing Operation Diagram for High Sampling Performance
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