AD7864
Rev. D | Page 7 of 28
DB7
DB8
DB9
DB10
DB11
CLKIN
INT/EXT CLK
BUSY
FRSTDAT
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
A
CONVST
CS
RD
WR
SL1
SL2
SL3
SL4
H/S SEL
AGND
AVDD
VREF
VREFGND
V
IN
2A
V
IN
1B
V
IN
1A
ST
B
Y
AG
ND
V
IN
4B
V
IN
2B
AG
ND
V
IN
4A
EO
C
DB
0
DB
1
DB
3
DB
4
DB
5
DG
ND
V
DR
IV
E
DV
DD
DB
2
DB
6
V
IN
3B
V
IN
3A
PIN 1
AD7864
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17 18 19 20 21 22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
0
134
1-
0
03
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
BUSY
Busy Output. The busy output is triggered high by the rising edge of CONVST and remains high until conversion
is completed on all selected channels.
2
FRSTDATA
First Data Output. FRSTDATA is a logic output which, when high, indicates that the output data register pointer
3
CONVST
Convert Start Input. Logic input. A low-to-high transition on this input puts all track-and-holds into their hold
mode and starts conversion on the selected channels. In addition, the state of the channel sequence selection is
also latched on the rising edge of CONVST.
4
CS
Chip Select Input. Active low logic input. The device is selected when this input is active.
5
RD
Read Input. Active low logic input that is used in conjunction with CS low to enable the data outputs. Ensure the
WR pin is at logic high while performing a read operation.
6
WR
Write Input. A rising edge on the WR input, with CS low and RD high, latches the logic state on DB0 to DB3 into
the channel select register.
7 to 10
SL1 to SL4
Hardware Channel Select. Conversion sequence selection can also be made via the SL1 to SL4 pins if H/S SEL is
Logic 0. The selection is latched on the rising edge of CONVST. See the
section.
11
H/S SEL
Hardware/Software Select Input. When this pin is at Logic 0, the AD7864 conversion sequence selection is
controlled via the SL1 to SL4 input pins. When this pin is at Logic 1, the sequence is controlled via the channel
12
AGND
Analog Ground. General analog ground. Connect this AGND pin to the AGND plane of the system.
13 to 16
VIN4x, VIN3x
17
AGND
Analog Ground. Analog ground reference for the attenuator circuitry. Connect this AGND pin to the AGND plane
of the system.
18 to 21
VIN2x, VIN1x
22
STBY
Standby Mode Input. TTL-compatible input that is used to put the device into the power save or standby mode.
The STBY input is high for normal operation and low for standby operation.
23
VREFGND
Reference Ground. This is the ground reference for the on-chip reference buffer of the part. Connect the
VREFGND pin to the AGND plane of the system.
24
VREF
Reference Input/Output. This pin provides access to the internal reference (2.5 V ± 5%) and also allows the
internal reference to be overdriven by an external reference source (2.5 V). Connect a 0.1 μF decoupling
capacitor between this pin and AGND.
25
AVDD
Analog Positive Supply Voltage, 5.0 V ± 5%.
26
AGND
Analog Ground. Analog ground reference for the DAC circuitry.