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参数资料
| 型号： | AD7866ARUZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 22/24页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 2CHAN DUAL 20TSSOP |
| 标准包装： | 1,000 |
| 位数： | 12 |
| 采样率（每秒）： | 1M |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 24mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 4 个单端，单极 |
| 配用： | EVAL-AD7866CBZ-ND - BOARD EVALUATION AD7866 |
REV. A
AD7866
–7–
PIN FUNCTION DESCRIPTIONS (continued)
Pin No.
Mnemonic
Function
11
RANGE
Analog Input Range and Output Coding Selection. Logic input. The polarity on this pin will
determine what input range the analog input channels on the AD7866 will have, and will also select
the type of output coding the ADC will use for the conversion result. On the falling edge of
CS, the
polarity of this pin is checked to determine the analog input range of the next conversion. If this pin
is tied to a logic low, the analog input range is 0 V to VREF and the output coding from the part will
be straight binary (for the next conversion). If this pin is tied to a logic high when
CS goes low, the
analog input range is 2
VREF and the output coding for the part will be twos complement. How-
ever, if after the falling edge of
CS the logic level of the RANGE pin has changed upon the eighth
SCLK falling edge, the output coding will change to the other option without any change in the
analog input range. (See the Analog Input and ADC Transfer Function sections.)
12
AVDD
Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on the
AD7866. The AVDD and DVDD voltages ideally should be at the same potential and must not be
more than 0.3 V apart even on a transient basis. This supply should be decoupled to AGND.
13
DVDD
Digital Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for all digital circuitry on the
AD7866. The DVDD and AVDD voltages should ideally be at the same potential and must not be
more than 0.3 V apart even on a transient basis. This supply should be decoupled to DGND.
14
DGND
Digital Ground. This is the ground reference point for all digital circuitry on the AD7866. The
DGND and AGND voltages ideally should be at the same potential and must not be more than 0.3 V
apart even on a transient basis.
15, 16
DOUTA, DOUTB
Serial Data Outputs. The data output is supplied to this pin as a serial data stream. The bits are
clocked out on the falling edge of the SCLK input. The data appears on both pins simultaneously
from the simultaneous conversions of both ADCs. The data stream consists of one leading zero
followed by three STATUS bits, followed by the 12 bits of conversion data. The data is provided
MSB first. If
CS is held low for another 16 SCLK cycles after the conversion data has been output
on either DOUTA or DOUTB, the data from the other ADC follows on the DOUT pin. This allows data
from a simultaneous conversion on both ADCs to be gathered in serial format on either DOUTA or
DOUTB alone using only one serial port. See the Serial Interface section.
17
VDRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface
will operate. This pin should be decoupled to DGND.
18
SCLK
Serial Clock. Logic Input. A serial clock input provides the SCLK for accessing the data from the
AD7866. This clock is also used as the clock source for the conversion process.
19
CS
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on
the AD7866 and frames the serial data transfer.
20
A0
Multiplexer Select. Logic input. This input is used to select the pair of channels to be converted
simultaneously, i.e., Channel 1 of both ADC A and ADC B, or Channel 2 of both ADC A and ADC B.
The logic state of this pin is checked upon the falling edge of
CS, and the multiplexer is set up for
the next conversion. If it is low, the following conversion will be performed on Channel 1 of each ADC;
if it is high, the following conversion will be performed on Channel 2 of each ADC.
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