参数资料
型号: AD7875BQ
厂商: Analog Devices Inc
文件页数: 8/28页
文件大小: 0K
描述: IC ADC 12BIT SAMPLING 5V 24CDIP
产品变化通告: Conversion Time Change
标准包装: 1
位数: 12
采样率(每秒): 100k
数据接口: 串行,并联
转换器数目: 1
功率耗散(最大): 95mW
电压电源: 双 ±
工作温度: -40°C ~ 85°C
安装类型: 通孔
封装/外壳: 24-CDIP(0.300",7.62mm)
供应商设备封装: 24-CDIP
包装: 管件
输入数目和类型: 1 个单端,单极
AD7870/AD7875/AD7876
Rev. C | Page 16 of
28
CS
TRACK-AND-HOLD
GOES INTO HOLD
TRACK-AND-HOLD RETURNS TO TRACK
AND ACQUISITION TIME BEGINS
THREE-STATE
VALID
DATA
DB11 TO DB0
RD
BUSY
DATA
t15
t17
t7
07
73
0-
01
6
t16
tCONVERT
t18
Figure 16. Mode 2 Timing Diagram, 12-Bit Parallel Read
CS
RD
BUSY
SSTRB2
DATA
SCLK3
TRACK-AND-HOLD RETURNS TO TRACK
AND ACQUISITION TIME BEGINS
TRACK-AND-HOLD
GOES INTO HOLD
THREE-STATE
LEADING
ZEROS
VALID
DATA
DB7 TO DB0
VALID
DATA
DB11 TO DB8
HBEN1
SDATA2
1TIMES
t15, t16, AND t20 ARE THE SAME FOR A HIGH BYTE READ AS FOR A LOW BYTE READ.
2EXTERNAL 4.7k PULL-UP RESISTOR.
3EXTERNAL 2k PULL-UP RESISTOR;
CONTINUOUS SCLK (DASHED LINE) WHEN 12/8/CLK = –5V;
NONCONTINUOUS WHEN 12/8/CLK = 0V.
DB11 DB10
SERIAL DATA
DB0
t8
t2
t18
t20
t7
t6
t7
t6
t17
t11
t10
t16
t15
t19
tCONVERT
t13
t14
t12
0
77
30
-01
7
Figure 17. Mode 2 Timing Diagram, Byte or Serial Read
The Mode 2 timing diagram for byte and serial data is shown in
Figure 17. For a two-byte data read, the lower byte (DB0 – DB7)
has to be accessed first since HBEN must be low to start conver-
sion. The ADC behaves like slow memory for this first read,
but the second read to access the upper byte of data is a normal
read. Operation of the serial functions is identical between
Mode 1 and Mode 2. The timing diagram of Figure 17 shows
both a noncontinuously and a continuously running SCLK
(dashed line).
DYNAMIC SPECIFICATIONS
The AD7870 and AD7875 are specified and 100% tested for
dynamic performance specifications as well as traditional dc
specifications such as integral and differential nonlinearity.
Although the AD7876 is not production tested for ac
parameters, its dynamic performance is similar to the AD7870
and AD7875. The ac specifications are required for signal
processing applications such as speech recognition, spectrum
analysis and high speed modems. These applications require
information on the ADC’s effect on the spectral content of the
input signal. Thus, the parameters for which the AD7870 and
AD7875 are specified include SNR, harmonic distortion,
intermodulation distortion and peak harmonics. These terms
are discussed in more detail in the following sections.
Signal-to-Noise Ratio (SNR)
SNR is the measured signal-to-noise ratio at the output of the
ADC. The signal is the rms magnitude of the fundamental.
Noise is the rms sum of all the nonfundamental signals up
to half the sampling frequency (FS/2) excluding dc. SNR is
dependent upon the number of quantization levels used in
the digitization process; the more levels, the smaller the
quantization noise. The theoretical signal-to-noise ratio for
a sine wave input is given by
SNR = (6.02N + 1.76) dB
(1)
where N is the number of bits. Thus for an ideal 12-bit
converter, SNR = 74 dB.
Note that a sine wave signal is of very low distortion to the VIN
input which is sampled at a 100 kHz sampling rate. A fast
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